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| flexray communication freescale.com controllers mfr4300 data sheet mfr4300 rev. 3 04/2007
mfr4300 data sheet mfr4300 rev. 3 04/2007 mfr4300 data sheet, rev. 3 4 freescale semiconductor to provide the most up-to-date information, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify that you have the latest information available, refer to http://www.freescale.com/flexray. the following revision history ta ble summarizes changes containe d in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) 3/2006 0 initial release - preliminary. n/a 4/2006 1 official release chapter 3 revised extensively. minor changes to other chapters. n/a 11/2006 2 ta bl e 1 - 1 : added definitions for id and phy ta bl e 2 - 3 : changed int_cc# reset value from 1 to 0 ta bl e 6 - 3 : corrected ecs bit description (actions defined by 0 and 1 were reversed). figure 6-6 : removed glitch from reset# waveform. ta bl e a - 9 : changed maximum value of v pord from 2.05 to 2.07. ta bl e a - 1 1 : changed ?por release level? to ?por deassert level?. ta bl e a - 1 1 : changed ?v porr ? to ?v pord ?. ta bl e a - 1 1 , a.3.1.1 , a.3.1.2 , a.3.1.2 , ta bl e a - 1 2 : updated to remove information relating to clock quality check block. updated mechanical outline drawing in figure b-1 , figure b-2 , and figure b-3 from rev. d to rev. e (to corre ct coplanarity specification). applied latest version of back page. fixed inconsistencies in naming conventions for ranges and active-low signal names. added ?write any time? field to register diagrams in pim and crg chapters. rotated text where appropriate in register diagrams to prevent line-breaks in bit names. 26 37 223 227 246 248 248 248 , 249 255 , 256 , and 257 various various various 04/2007 3 corrected any unresolved cross-references. inserted ?ac over or undershoots for +/-2v beyond the supply if limited to 20ns length are allowed.? as a footnote for ta bl e a - 1 . corrected hyphens, em dashes, and en dashes for appendix. various 239 various mfr4300 data sheet, rev. 3 freescale semiconductor 5 introduction device overview flexray module (flexrayv2) port integration module (pim) dual output voltage regulator (vreg3v3v2) clocks and reset generator (crg) oscillator (oscv2) electrical characteristics package information printed circuit board layout recommendations index of registers mfr4300 data sheet, rev. 3 6 freescale semiconductor mfr4300 data sheet, rev. 3 freescale semiconductor 7 contents section number title page chapter 1 introduction 1.1 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 additional reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 part number coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 chapter 2 device overview 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.1 mfr4300 implementation parameters an d constraints . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.3.2 part id and module version number assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.1 system pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.2 pin functions and signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.3 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 2.4.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6 external clock and host interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.1 external 4/10/40 mhz output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.2 external host interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.6.3 recommended pullup/pulldown resistor values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.7 external host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.7.1 asynchronous memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.7.2 hcs12 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.8 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.8.1 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.8.2 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 chapter 3 flexray module (flexrayv2) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.1 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.2 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.3 color coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 mfr4300 data sheet, rev. 3 8 freescale semiconductor section number title page 3.1.4 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.5 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.2.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 3.3 memory map and register desc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 3.4.1 message buffer concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 3.4.2 physical message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 33 3.4.3 message buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 3.4.4 flexray memory layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 3.4.5 physical message buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 3.4.6 individual message buffer functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 3.4.7 individual message buffer search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 3.4.8 individual message buffer reconfigur ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 3.4.9 receive fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 3.4.10 channel device modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 84 3.4.11 external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.4.12 sync frame id and sync frame deviation tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 3.4.13 mts generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 3.4.14 sync frame and startup frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.4.15 sync frame filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 3.4.16 strobe signal support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 3.4.17 timer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 3.4.18 slot status monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 3.4.19 interrupt support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 3.4.20 clock domain crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 01 3.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.5.1 flexray initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 3.5.2 number of usable message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 3.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.1 shut down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 03 3.6.2 protocol control command execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 3.6.3 protocol reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 chapter 4 port integration module (pim) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 mfr4300 data sheet, rev. 3 freescale semiconductor 9 section number title page 4.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 4.2.1 functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 4.2.2 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.3 pim memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 4.3.1 port integration module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.4.1 functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 4.4.2 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 chapter 5 dual output voltage regulator (vreg3v3v2) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 5.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 5.2.1 v ddr , v ssr ? regulator power input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 5.2.2 v dda , v ssa ? regulator reference supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 5.2.3 v dd , v ss ? regulator output1 (core logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.2.4 v ddosc , v ssosc ? regulator output2 (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.1 reg ? regulator core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.2 full-performance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 5.3.3 por ? power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 5.3.4 lvr ? low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.3.5 ctrl ? regulator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.4 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.4.1 power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.4.2 low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 chapter 6 clocks and reset generator (crg) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 6.2 mfr4300 relevant pins for the crg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3 crg registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3.1 detection enable register (der) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 6.3.2 clock and reset status register (crsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 6.4.1 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 mfr4300 data sheet, rev. 3 10 freescale semiconductor section number title page 6.4.2 interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 6.4.3 clkout mode selection and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 chapter 7 oscillator (oscv2) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.2.1 v ddosc and v ssosc ? osc operating voltage, osc ground . . . . . . . . . . . . . . . . . . 233 7.2.2 extal and xtal ? clock/crystal source pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 7.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.4.1 clock monitor (cm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 7.5 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 appendix a electrical characteristics a.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 a.1.4 current injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 a.2 voltage regulator (vreg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 a.2.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 a.2.2 chip power-up and voltage drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 a.2.3 output loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 a.3 reset and oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 a.3.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 a.3.2 oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 a.4 asynchronous memory interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 0 a.5 hcs12 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 mfr4300 data sheet, rev. 3 freescale semiconductor 11 section number title page appendix b package information b.1 64-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 appendix c printed circuit board layout recommendations appendix d index of registers mfr4300 data sheet, rev. 3 12 freescale semiconductor section number title page mfr4300 data sheet, rev. 3 freescale semiconductor 13 list of figures figure number title page figure 1-1. order part number coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 2-1. mfr4300 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 2-2. mfr4300 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 2-3. oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 2-4. external square wave clock generator connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 2-5. ami interface with mpc5xx a nd mpc55xx families . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 2-6. ami interface with s12x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 2-7. ami interface with dsp 56f83 (hawk) family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 2-8. hcs12 interface address deco ding and internal chip select generation . . . . . . . . . . . 53 figure 2-9. hcs12 interface with hcs12 pa ge mode support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 2-10. hcs12 interface with hcs12 u npaged mode support . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 3-1. flexray module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 3-2. module version register (mvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3-3. module configuration re gister (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 3-4. strobe signal control register (stbscr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 3-5. strobe port control register (stbpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 3-6. message buffer data size regist er (mbdsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 3-7. message buffer segment si ze and utilization register (mbssutr ). . . . . . . . . . . . . . . 74 figure 3-8. protocol operation control regi ster (pocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 3-9. global interrupt flag and enab le register (gifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 3-10. protocol interrupt flag register 0 (pifr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 3-11. protocol interrupt flag register 1 (pifr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 3-12. protocol interrupt enable register 0 (pier0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 3-13. protocol interrupt enable register 1 (pier1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 3-14. chi error flag register (chierfr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 3-15. message buffer inte rrupt vector register (mbivec). . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 3-16. channel a status error counter register (casercr) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 3-17. channel b status error counter register (cbsercr) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 3-18. protocol status regist er 0 (psr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 3-19. protocol status regist er 1 (psr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 3-20. protocol status regist er 2 (psr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 3-21. protocol status regist er 3 (psr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 mfr4300 data sheet, rev. 3 14 freescale semiconductor figure number title page figure 3-22. macrotick counter regi ster (mtctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 3-23. cycle counter register (cyctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 figure 3-24. slot counter channel a regist er (sltctar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 3-25. slot counter channel b regist er (sltctbr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 3-26. rate correction value register (rtcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 3-27. offset correction value regist er (ofcorvr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 3-28. combined interrupt flag register (cifrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 3-29. sync frame counter register ( sfcntr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 3-30. sync frame table offs et register (sftor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 3-31. sync frame table configur ation, control, status register (s ftccsr). . . . . . . . . . . . . 99 figure 3-32. sync frame id reje ction filter register (sfidrfr) . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 3-33. sync frame id acceptance filter value register (sfidafvr). . . . . . . . . . . . . . . . . . 101 figure 3-34. sync frame id acceptance filter mask register (sfidafmr). . . . . . . . . . . . . . . . . . 101 figure 3-35. network management vector registers (nmvr0?nmvr5) . . . . . . . . . . . . . . . . . . . . 101 figure 3-36. network management vector length register (nmvlr) . . . . . . . . . . . . . . . . . . . . . . 102 figure 3-37. timer configuration and contro l register (ticcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 3-38. timer 1 cycle set register (ti1cysr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 3-39. timer 1 macrotick offset regi ster (ti1mtor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 3-40. timer 2 configuration register 0 (ti2cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 3-41. timer 2 configuration register 1 (ti2cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 3-42. slot status selecti on register (sssr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 figure 3-43. slot status counter condition register (ssccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 3-44. slot status registers (ssr0?ssr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 3-45. slow status counter registers (sscr0?sscr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 3-46. mts a configuration register (mtsacfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 3-47. mts b configuration register (mtsbcfr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 3-48. receive shadow buffer index register (rsbir). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 3-49. receive fifo selecti on register (rfsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 3-50. receive fifo start index regist er (rfsir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 3-51. receive fifo depth and size register (rfdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 3-52. receive fifo a read index re gister (rfarir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 3-53. receive fifo b read index re gister (rfbrir). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 3-54. receive fifo me ssage id acceptance filter value re gister (rfmidafvr). . . . . . . 115 figure 3-55. receive fifo me ssage id acceptance filter mask re gister (rfmiafmr) . . . . . . . . 116 figure 3-56. receive fifo frame id re jection filter value register (r ffidrfvr) . . . . . . . . . . . 116 mfr4300 data sheet, rev. 3 freescale semiconductor 15 figure number title page figure 3-57. receive fifo frame id rejection filter mask register (rffidrfmr) . . . . . . . . . . . 117 figure 3-58. receive fifo range filter configuration register (rfrfcfr) . . . . . . . . . . . . . . . . . 117 figure 3-59. receive fifo range filter control register (rfrfctr) . . . . . . . . . . . . . . . . . . . . . . 118 figure 3-60. last dynamic slot channel a register (ldtxslar) . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 3-61. last dynamic slot channel b register (ldtxslbr) . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 3-62. protocol configuration register 0 (pcr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 3-63. protocol configuration register 1 (pcr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 3-64. protocol configuration register 2 (pcr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 3-65. protocol configuration register 3 (pcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 3-66. protocol configuration register 4 (pcr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 3-67. protocol configuration register 5 (pcr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 3-68. protocol configuration register 6 (pcr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 3-69. protocol configuration register 7 (pcr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 3-70. protocol configuration register 8 (pcr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 3-71. protocol configuration register 9 (pcr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 3-72. protocol configuration register 10 (pcr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 3-73. protocol configuration register 11 (pcr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 3-74. protocol configuration register 12 (pcr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 3-75. protocol configuration register 13 (pcr13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 3-76. protocol configuration register 14 (pcr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 3-77. protocol configuration register 15 (pcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 3-78. protocol configuration register 16 (pcr16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 3-79. protocol configuration register 17 (pcr17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 3-80. protocol configuration register 18 (pcr18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 3-81. protocol configuration register 19 (pcr19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 3-82. protocol configuration register 20 (pcr20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 3-83. protocol configuration register 21 (pcr21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 3-84. protocol configuration register 22 (pcr22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 3-85. protocol configuration register 23 (pcr23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 3-86. protocol configuration register 24 (pcr24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 3-87. protocol configuration register 25 (pcr25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 3-88. protocol configuration register 26 (pcr26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 3-89. protocol configuration register 27 (pcr27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 3-90. protocol configuration register 28 (pcr28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 3-91. protocol configuration register 29 (pcr29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mfr4300 data sheet, rev. 3 16 freescale semiconductor figure number title page figure 3-92. protocol configuration register 30 (pcr30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 3-93. message buffer configurat ion, control, status registers (m bccsrn) . . . . . . . . . . . . 128 figure 3-94. message buffer cycle coun ter filter registers (mbccfrn) . . . . . . . . . . . . . . . . . . . . 130 figure 3-95. message buffer frame id regi sters (mbfidrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 3-96. message buffer index register s (mbidxrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 3-97. physical message buffer structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 33 figure 3-98. individual message buffer struct ure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 figure 3-99. receive shadow buffer structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 36 figure 3-100. receive fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 3-101. example of frm layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 3-102. frame header structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 3-103. receive message buffer slot status structure (chab) . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 3-104. receive message buffer slot st atus structure (cha) . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 3-105. receive message buffer slot st atus structure (chb) . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 3-106. transmit message buffer slot status structure (chab) . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 3-107. transmit message buffer slot status structure (cha) . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 3-108. transmit message buffer slot status structure (chb). . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 3-109. message buffer data field structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 50 figure 3-110. single transmit message buffer access regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 3-111. single transmit message buffer states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 3-112. message transmis sion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 3-113. message transmission from hlck state with unlock. . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 3-114. null frame transmission from idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 3-115. null frame transmission from hlck state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 3-116. null frame transmission from hlck state with unlock . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 3-117. null frame transmission from with locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 3-118. receive message buffe r access regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 3-119. receive message buffer states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 figure 3-120. message reception timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 3-121. double transmit buffer structur e and data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 3-122. double transmit message bu ffer access regions layout . . . . . . . . . . . . . . . . . . . . . . 168 figure 3-123. double transmit message buffer state diagra m (commit side) . . . . . . . . . . . . . . . . . 170 figure 3-124. double transmit message buffer state diagra m (transmit side). . . . . . . . . . . . . . . . . 171 figure 3-125. internal message transfer in streaming co mmit mode . . . . . . . . . . . . . . . . . . . . . . . . 175 figure 3-126. internal message transfer in immediate commit mode . . . . . . . . . . . . . . . . . . . . . . . . 175 mfr4300 data sheet, rev. 3 freescale semiconductor 17 figure number title page figure 3-127. inconsistent channel assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 3-128. message buffer reconfiguration scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 3-129. received frame fifo filter path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 3-130. dual channel device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 3-131. single channel device mode (channel a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 3-132. single channel device mode (channel b). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 3-133. external offset correction write and application timing . . . . . . . . . . . . . . . . . . . . . . 186 figure 3-134. external rate correction wr ite and application timing . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 3-135. sync table memory layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 3-136. sync frame table trigger and generation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 figure 3-137. strobe signal timing (type = pul se, clk_offset = -2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 3-138. strobe signal timing (type = pulse, clk_offset = +4) . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 3-139. slot status vector update. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 3-140. slot status counting and sscrn update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 figure 3-141. scheme of cascaded interrupt re quest. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 99 figure 3-142. int_cc# generation scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 3-143. scheme of combined interrupt fl ags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 00 figure 4-1. part id register (pidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 4-2. asic version number register (avnr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 4-3. host interface pins drive st rength register (hipdsr) . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 4-4. physical layer pins drive strength register (p lpdsr) . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 4-5. host interface pins pullup/ pulldown enable register (hipper) . . . . . . . . . . . . . . . . . 209 figure 4-6. host interface pins pullup/ pulldown control register (hippcr) . . . . . . . . . . . . . . . . . 211 figure 4-7. physical layer pins pull up/pulldown enable register (plpper) . . . . . . . . . . . . . . . . . 212 figure 4-8. physical layer pins pullup/pulldown control register (plppcr) . . . . . . . . . . . . . . . . 213 figure 5-1. vreg3v3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 figure 6-1. detection enable register (der). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2 figure 6-2. clock and reset status register (crsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 6-3. crg power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 6-4. low voltage reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 6-5. clock monitor failure reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 6-6. external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 6-7. interface selection during power-on or low voltage reset or clock monitor failure. 227 figure 6-8. interface selection during extern al reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 mfr4300 data sheet, rev. 3 18 freescale semiconductor figure number title page figure 6-9. clkout mode selection and contro l during low-voltage reset or clock monitor failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 6-10. clkout mode selection and control during ex ternal reset . . . . . . . . . . . . . . . . . . . 230 figure 6-11. clkout mode selection and control during power-on reset . . . . . . . . . . . . . . . . . . 231 figure a-1. voltage regulator ? chip power-up and volt age drops (not scaled) . . . . . . . . . . . . . 248 figure a-2. ami interface read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure a-3. ami interface write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure a-4. hcs12 interface read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 figure a-5. hcs12 interface write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 figure b-1. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 1) . . . . . . . . . . . . . . . . 255 figure b-2. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 2) . . . . . . . . . . . . . . . . 256 figure b-3. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 3) . . . . . . . . . . . . . . . . 257 figure c-1. recommended pcb layout (64-pin lqfp) fo r standard pierce oscillator mode . . . . 260 mfr4300 data sheet, rev. 3 freescale semiconductor 19 list of tables table number title page table 1-1. acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 1-2. notational conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 2-1. mfr4300 device memory map after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 2-2. part id and module version number s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 2-3. pin functions and signa l properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 2-4. mfr4300 power and ground connecti on summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 2-5. clkout frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 2-6. interface selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 2-7. recommended pullup and pulldown resistor va lues for if_sel[1:0] inputs . . . . . . . . . 47 table 2-8. ami access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 2-9. hcs12 access types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 3-1. list of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 3-2. external signal properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 3-3. flexray memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 3-4. register access conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 3-5. additional register reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 3-6. register write access restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 3-7. mvr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 3-8. mcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 3-9. channel enable mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 3-10. stbscr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 3-11. strobe signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 3-12. stbpcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 3-13. mbdsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 3-14. mbssutr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 3-15. pocr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 3-16. gifer field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 3-17. pifr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 3-18. pifr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 3-19. pier0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 3-20. pier1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 3-21. chierfr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 mfr4300 data sheet, rev. 3 20 freescale semiconductor table number title page table 3-22. mbivec field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 3-23. casercr field descrip tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 3-24. cbsercr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 3-25. psr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 3-26. psr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 3-27. psr2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 3-28. psr3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 3-29. mtctr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 3-30. cyctr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 3-31. sltctar field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 3-32. sltctbr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 3-33. rtcorvr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 3-34. ofcorvr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 3-35. cifrr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 3-36. sfcntr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 3-37. sftor field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 3-38. sftccsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 3-39. sfidrfr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 3-40. sfidafvr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 3-41. sfidafmr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 01 table 3-42. nmvr[0:5] field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 3-43. mapping of nmvrn to the re ceived payload bytes nmvn. . . . . . . . . . . . . . . . . . . . . . 102 table 3-44. nmvlr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 3-45. ticcr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 3-46. ti1cysr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 3-47. ti1mtor field descript ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 3-48. ti2cr0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 3-49. ti2cr1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 3-50. sssr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 3-51. mapping between sssrn and ssrn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 3-52. ssccr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 3-53. mapping between internal ssccr n and sscrn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 3-54. ssr0?ssr7 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 3-55. sscr0?sscr3 field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 3-56. mtsacfr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 mfr4300 data sheet, rev. 3 freescale semiconductor 21 table number title page table 3-57. mtsbcfr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 3-58. rsbir field descripti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 3-59. sel controlled receiver fifo registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 3-60. rfsr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 3-61. rfsir field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 3-62. rfdsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 3-63. rfarir field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 3-64. rfbrir field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 3-65. rfmidafvr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 3-66. rfmiafmr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 table 3-67. rffidrfvr field descri ptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 16 table 3-68. rffidrfmr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 table 3-69. rfrfcfr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 3-70. rfrfctr field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 3-71. ldtxslar field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 19 table 3-72. ldtxslbr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 19 table 3-73. protocol configuration register fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 19 table 3-74. wakeup channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 3-75. mbccsrn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 3-76. mbccfrn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 3-77. channel assignment description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 3-78. mbfidrn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 3-79. mbidxrn field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 3-80. frame header write access constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 3-81. frame header field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 3-82. receive message buffer slot status content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 3-83. receive message buffer slot st atus field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 3-84. transmit message buffer slot status content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 3-85. transmit message buffer slot status structure field descriptions . . . . . . . . . . . . . . . . . 148 table 3-86. message buffer data field mi nimum length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 3-87. frame data write access constrai nts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 3-88. frame data field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 3-89. individual message buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 3-90. single transmit message buff er access regions description. . . . . . . . . . . . . . . . . . . . . 153 table 3-91. single transmit message buffer state description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 mfr4300 data sheet, rev. 3 22 freescale semiconductor table number title page table 3-92. single transmit message buffer application transitions . . . . . . . . . . . . . . . . . . . . . . . . 155 table 3-93. single transmit message buffer module transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 3-94. single transmit message buffer transition priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 3-95. receive message buffe r access region description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 3-96. receive message buffer states a nd access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 3-97. receive message buffe r application transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 3-98. receive message buffe r module transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 3-99. receive message buffer transition priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 3-100. receive message buffer update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 3-101. double transmit message buff er access regions description . . . . . . . . . . . . . . . . . . . . 169 table 3-102. double transmit message buffer state descri ption (commit side) . . . . . . . . . . . . . . . . 170 table 3-103. double transmit message buffer state descri ption (transmit side) . . . . . . . . . . . . . . . 171 table 3-104. double transmit message buffer host transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 3-105. double transmit message buff er module transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 3-106. double transmit message buffer transition priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 3-107. message buffer search priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 3-108. sync frame table gene ration modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 3-109. slot status content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 3-110. minimum chi frequency examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 3-111. protocol control command priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 04 table 4-1. pin functions (f unctional mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 4-2. pin functions (reset m ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 4-3. port integration module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 4-4. hipdsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 4-5. plpdsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 4-6. hipper field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 4-7. hippcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 table 4-8. plpper field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 table 4-9. plppcr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 5-1. vreg3v3v2 ? signal properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 5-2. vreg3v3v2 ? reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 table 6-1. mfr4300 relevant pins for the crg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 6-2. der field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 6-3. crsr field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 6-4. crg reset sources priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 mfr4300 data sheet, rev. 3 freescale semiconductor 23 table number title page table 6-5. if_sel[1:0] encoding by crsr.ecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table a-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table a-2. esd and latch-up test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 0 table a-3. esd and latch-up protection char acteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 table a-4. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 table a-5. thermal package simulation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table a-6. 5v i/o characteristics (vdd5 = 5v ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table a-7. 3.3v i/o characteristics (vdd5 = 3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table a-8. supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table a-9. voltage regulator ? operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 table a-10. voltage regulator recommended capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table a-11. startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table a-12. oscillator characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table a-13. ami interface ac switching characteristics over the operating range . . . . . . . . . . . . 252 table a-14. hcs12 interface ac switching characteristic s over the operating range . . . . . . . . . . 254 table c-1. suggested external component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 mfr4300 data sheet, rev. 3 24 freescale semiconductor table number title page mfr4300 data sheet, rev. 3 freescale semiconductor 25 chapter 1 introduction this data sheet provides information on a system that includes the mfr4300 flexray communication controller module. 1.1 audience this data sheet is intended for appl ication and system hardware devel opers who wish to develop products for the flexray mfr4300. it is assumed that the re ader understands flexray protocol functionality and microcontroller system design. 1.2 additional reading for additional reading that provide s background to, or supplements, th e information in this manual: ? for more information about the flexray protocol, refer to the following document: ? flexray communications system protocol specification v2.1 ? flexray communications system electr ical physical layer specification v2.1 ? for more information about m9hcs12 family devices and m9 hcs12 programming, refer to the freescale products section at www.freescale.com . introduction mfr4300 data sheet, rev. 3 26 freescale semiconductor 1.3 terminology table 1-1. acronyms and abbreviations term meaning ami asynchronous memory interface bcu buffer control unit cc communication controller cdc clock domain crosser chi controller host interface id identification ebi external bus interface frm flexray memory fss frame start sequence hif host interface lut look up table mbidx message buffer index mbnum message buffer number mcu microcontroller unit tmicrotick mt macrotick mts media access test symbol nit network idle time pe protocol engine phy physical layer interface pl physical layer poc protocol operation control seq sequencer engine rx reception tcu time control unit tx transmission introduction mfr4300 data sheet, rev. 3 freescale semiconductor 27 1.4 part number coding figure 1-1. order part number coding table 1-2. notational conventions active-high names of signals that are active-high are sh own in upper case text, without a ?#? symbol at the end. active-high signals are asserted (active) when they are high and deasserted when they are low. active-low a ?#? symbol at the end of a signal name indicates that the signal is active-low. an active-low signal is asserted (active) when it is at the logic low level and is deasserted when it is at the logic high level. asserted a signal that is asserted is in its active logic st ate. an active-low signal changes from high to low when asserted; an active-high signal changes from low to high when asserted. deasserted a signal that is deasserted is in its inactive logic state. an active-low signal changes from low to high when deasserted; an active-high signal changes from high to low when deasserted. set to set a bit means to establish logic level one on the bit. clear to clear a bit means to establish logic level zero on the bit. 0x0f the prefix ?0x? denotes a hexadecimal number. 0b0011 the prefix ?0b? denotes a binary number. x in certain contexts, such as a signal encoding, this indicates ?don?t care?. for example, if a field is binary encoded 0bx001, the state of the first bit is ?don?t care?. == used in equations, this symbol signifies comparison. p fr 4300 m ae 40 speed option temperature option device title controller family qualification package option m = qualified part 40 = 40 mhz ae = 64-pin lead free / halide free lqfp m = -40 o c to +125 o c p = engineering sample introduction mfr4300 data sheet, rev. 3 28 freescale semiconductor mfr4300 data sheet, rev. 3 freescale semiconductor 29 chapter 2 device overview 2.1 introduction the mfr4300 flexray communication controller implem ents the flexray protocol according to the flexray communications system protocol specification v2.1 . the controller host interface (chi ) of the mfr4300 flexray communicat ion controller is implemented in accordance with chapter 3, ?flexray module (flexrayv2)? of this data sheet. 2.2 features the mfr4300 flexray controller provides the following features: ? single channel support ? internal channel a and flexray po rt a can be configured to be connected either to physical flexray channel a or physical flexray channel b ? 128 configurable message buffers with ? individual frame id filtering ? individual channel id filtering ? individual cycle counter filtering ? message buffer header, status and payl oad data are stored in flexray memory ? consistent data access ensured by means of buffer locking scheme ? host can lock multiple buffers at the same time ? size of message buffer data section configurable from 0 up to 254 bytes ? two independent message buffer segments with configurable size of payload data section ? each segment can contain message buffers assign ed to the static segment and message buffers assigned to the dynamic segment at the same time ? zero padding for transmit messag e buffers in static segment ? applied when the frame payload length exceeds the size of the message buffer data section ? transmit message buffers configur able with state/event semantics ? message buffers can be configured as ? receive message buffers ? single buffered transmit message buffer ? double buffered transmit message buffer (c ombines two single buffered message buffer) ? individual message buffer r econfiguration supported ? means provided to safely di sable individual message buffers ? disabled message buffers can be reconfigured ? two independent receive fifos device overview mfr4300 data sheet, rev. 3 30 freescale semiconductor ? one receive fifo per channel ? up to 256 entries for each fifo ? global frame id filtering, based on both value/mask filters and range filters ? global channel id filtering ? global message id filter ing for the dynamic segment ? four configurable slot error counters ? four dedicated slot status indicators ? used to observe slots without using receive message buffers ? provides measured value indi cators for clock synchronization ? pe internal synchronization fram e id and measurement tables ca n be copied into the flexray memory ? fractional macroticks are supported for clock correction ? maskable interrupt sources provided throu gh individual and combined interrupt lines ? one absolute timer ? one timer that can be configured to absolute or relative features specific to the mf r4300 include the following: ? two hardware selectable host interfaces: ? hcs12 interface for direct connection to freesc ale?s hcs12 family of microcontrollers, with interface clock signal to synchronize the data tr ansfer (the maximum frequency of this clock signal can be calculated from the ec lk pulse width low and high times, t lec and t hec given in table a-14 .) ? asynchronous memory interface (ami) for as ynchronous connection to microcontrollers ? minimum read access time of 53 ns (with chiclk_cc running at 80 mhz) ? 8k bytes addressable for byte or word accesses ? internal quartz oscillator of 40 mhz ? chi and ami clock selectable between 40 mhz oscillator clock used for pe and 20 mhz to 80 mhz separate chi/ami-only clock ? internal voltage regulator for th e digital logic and the oscillator ? hardware selectable clock output to drive ex ternal host devices: di sabled, 4, 10, or 40 mhz ? maskable interrupt sources availa ble over one interrupt output line ? electrical physical layer in terface compatible with dedi cated flexray physical layer ? four multiplexed debug strobe pins 2.2.1 mfr4300 implementation parameters and constraints 2.2.1.1 implementation parameters ? the duration of a microtick (t) is one clk_cc period (25 ns at 40 mhz). ? a microtick starts with the rising edge of clk_cc. device overview mfr4300 data sheet, rev. 3 freescale semiconductor 31 2.2.1.2 implementation constraints ? the external clock frequency for extal/clk_cc is 40 mhz. ? the minimum external clock frequency for chiclk_cc (when selected) is 20 mhz. ? the maximum external clock fr equency for chiclk_cc is 80 mhz device overview mfr4300 data sheet, rev. 3 32 freescale semiconductor 2.3 block diagram figure 2-1. mfr4300 functional block diagram voltage regulator vssr vdda vssa vddr vss2_5 vdd2_5 oscillator clock and reset gen. module reset# external clock interface clkout/tm0 d0/pa7 d1/pa6 d2/pa5 d3/pa4 d4/pa3 d5/pa2 d6/pa1 d7/pa0 d8/pb7 d9/pb6 d10/pb5 d11/pb4 d12/pb3 d13/pb2 d14/pb1 d15/pb0 external bus interface ami hcs12 interface a1/xaddr19 a2/xaddr18 a3/xaddr17 a4/xaddr16 a5/xaddr15 a6/xaddr14 a7 a8 a9 oe#/acs0 a11/acs1 a12/acs2 we#/rw_cc# ce#/lstrb a10/eclk_cc int_cc# receiver a receiver b rxd_bg2 rxd_bg1 transmitter a transmitter b txd_bg1/if_sel1 txen1# txd_bg2/if_sel0 txen2# dbg3/clk_s1 tcu debug test vddx[1:4] vssx[1:4] xtal extal/clk_cc vddosc vssosc bsel0#/dbg1 bsel1#/dbg0 dbg2/clk_s0 chiclk_cc flexray module device overview mfr4300 data sheet, rev. 3 freescale semiconductor 33 2.3.1 memory map table 2-1 shows the mfr4300 device memory map. table 2-1. mfr4300 device memory map after reset address (hex) module registers size (bytes) 0x0000?0x000e flexray 1 1 for detailed information on the mfr4300 flexray module registers, see chapter 3, ?flexray module (flexrayv2)? . configuration and control registers 16 0x0010?0x0012 flexray reserved 4 0x0014?0x0026 flexray interrupt and error handling registers 20 0x0028?0x003e flexray protocol status registers 24 0x0040?0x0044 flexray sync frame counter and table registers 6 0x0046?0x004a flexray sync frame filter registers 6 0x004c?0x0058 flexray network m anagement vector registers 14 0x005a?0x0062 flexray timer configuration registers 10 0x0064?0x0066 flexray slot status configuration registers 4 0x0068?0x007e flexray slot status and sl ot status counter registers 24 0x0080?0x0082 flexray mts generation registers 4 0x0084 flexray shadow buffer configuration register 2 0x0086?0x008a flexray receive fifo ? configuration 6 0x008c?0x008e flexray receive fifo ? status 4 0x0090?0x009a flexray receive fifo ? filter 12 0x009c, 0x009e flexray dynamic segment status registers 4 0x00a0?0x00de flexray protocol configuration registers 64 0x00e0?0x00e2 crg 2 2 for detailed information on the mfr4300 crg module registers, see chapter 6, ?clocks and reset generator (crg)? . clock and reset generation registers 4 0x00e4?0x00ee flexray reserved 12 0x00f0?0x00fe pim 3 3 for detailed information on the mfr4300 pim module registers, see chapter 4, ?port integration module (pim)? . part id, asic version number, and interface pin drive strength and pullup/pulldown control and enable registers 16 0x0100?0x01fe flexray message buffers configuratio n, control, status (message buffer 0?31) 256 0x0200?0x02fe flexray message buffers configuratio n, control, status (message buffer 32?63) 256 0x0300?0x03fe flexray message buffers configuratio n, control, status (message buffer 64?95) 256 0x0400?0x04fe flexray message buffers configuratio n, control, status (message buffer 96?127) 256 0x0500?0x07fe flexray reserved 768 0x0800?0x1ffe flexray message buffers and fifo frame header/offset/status/data 6144 device overview mfr4300 data sheet, rev. 3 34 freescale semiconductor 2.3.2 part id and module ve rsion number assignments three 16-bit read-only registers provide information about the de vice and the mfr4300 flexray module (see table 2-2 ). the pidr (see section 4.3.1.1, ?part id register (pidr) ?) provides the part id number in binary coded decimal (in this case, ?4300?) the avnr (see section 4.3.1.2, ?asic version number register (avnr) ?) provides the asic version number in binary coded decimal (in this case, ?0000?). the mvr (see section 3.3.2.3, ?module version register (mvr) ?) provides the flexray module version number in binary coded decimal (in this case, ?3535?). bits 15 to 8 of the mvr comprise the controller host interface (chi) version number; bits 7 to 0 comprise the prot ocol engine (pe) version number. these read-only values provide a unique id for each revisi on of the device. 2.4 signal descriptions 2.4.1 system pinout the mfr4300 is available in a 64-pin low profile qua d flat package (lqfp). most pins perform two functions, as described in section 2.4.2, ?pin functions and signal properties ?. figure 2-2 shows the pin assignments. note for a recommended printed circuit board layout, see appendix c, ?printed circuit board layout recommendations ?. table 2-2. part id and module version numbers device mask set number part id pidr avnr mvr mfr4300 0m92d 4300 0000 3535 device overview mfr4300 data sheet, rev. 3 freescale semiconductor 35 figure 2-2. mfr4300 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 test d9/pb6 d10/pb5 d11/pb4 d12/pb3 d13/pb2 d14/pb1 d15/pb0 vddx1 vssx1 a1/xaddr19 a2/xaddr18 a3/xaddr17 a4/xaddr16 a5/xaddr15 reset# int_cc# clkout d8/pb7 d7/pa0 vss2_5 vdd2_5 d6/pa1 d5/pa2 d4/pa3 d3/pa4 vddx3 a10/eclk_cc d2/pa5 vdda vssa vssx3 bsel1#/dbg0 bsel0#/dbg1 dbg3/clk_s1 txd_bg2/if_sel0 txen2# rxd_bg2 dbg2/clk_s0 txd_bg1/if_sel1 d1/pa6 d0/pa7 vssx2 vddx2 txen1# vddx4 a12/acs2 rxd_bg1 chiclk_cc xtal vssosc a9 a8 vddr vssr a7 a6/xaddr14 extal/clk_cc vddosc oe#/acs0 a11/acs1 ce#/lstrb we#/rw_cc# vssx4 device overview mfr4300 data sheet, rev. 3 36 freescale semiconductor 2.4.2 pin functions and signal properties table 2-3. pin functions and signal properties pin # pin name 1 powered by i/o pin type 2, 3 reset functional description function 1 function 2 host interface pins 11 a1 xaddr19 vddx i pc - ami address bus / hcs12 expanded address lines. a1-lsb of the ami address bus, xaddr14-lsb of the hcs12 expanded address lines 12 a2 xaddr18 vddx i pc - ami address bus / hcs12 expanded address lines. 13 a3 xaddr17 vddx i pc - ami address bus / hcs12 expanded address lines. 14 a4 xaddr16 vddx i pc - ami address bus / hcs12 expanded address lines. 15 a5 xaddr15 vddx i pc - ami address bus / hcs12 expanded address lines. 17 a6 xaddr14 vddx i pc - ami address bus / hcs12 expanded address lines. 18 a7 - vddx i pc - ami address bus 21 a8 - vddx i pc - ami address bus 22 a9 - vddx i pc - ami address bus 27 oe# acs0 vddx i pc - ami read output enable signal / hcs12 address select input 28 a11 acs1 vddx i pc - ami address bus / hcs12 address select inputs 34 a12 acs2 vddx i pc - ami address bus / hcs12 address select inputs 48 bsel1# dbg0 vddx i/o pc - ami byte select / debug strobe point 47 bsel0# dbg1 vddx i/o pc - ami byte select / debug strobe point 10 d15 pb0 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. d15 is the msb of the ami data bus, pb0 is the lsb of the hcs12 address/data bus 7 d14 pb1 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 6 d13 pb2 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 5 d12 pb3 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 4 d11 pb4 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 3 d10 pb5 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. 2 d9 pb6 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 62 d8 pb7 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 61 d7 pa0 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 58 d6 pa1 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 57 d5 pa2 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 56 d4 pa3 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus device overview mfr4300 data sheet, rev. 3 freescale semiconductor 37 55 d3 pa4 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 51 d2 pa5 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 40 d1 pa6 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus 39 d0 pa7 vddx i/o z/dc/pc z ami data bus / hcs12 multiplexed address/data bus. d0 is the lsb of the ami data bus, pa7 is the msb of the hcs12 address/data bus 29 ce# lstrb vddx i pc - ami chip select si gnal / hcs12 low-byte strobe signal 30 we# rw_cc# vddx i pc - ami write enable signal/ hcs12 read/write select signal 52 a10 eclk_cc vddx i pc - ami address bus/ hcs12 clock input physical layer interface 33 rxd_bg1 - vddx i pc - phy data receiver input 43 rxd_bg2 - vddx i pc - phy data receiver input 36 txen1# - vddx o dc 1 transmit enable for phy 44 txen2# - vddx o dc 1 transmit enable for phy 45 txd_bg2 if_sel0 vddx i/o dc/pd - phy data tr ansmitter output / host interface select 41 txd_bg1 if_sel1 vddx i/o dc/pd - phy data tr ansmitter output / host interface select clock signals 32 chiclk_cc - vddx i - - external chi clock input ? selectable 63 clkout - vddx i/o dc - controller clock output ? selectable as disabled/4/10/40 mhz others 16 reset# - vddx i - - external hardware reset input 64 int_cc# - vddx o od/dc 0 controller interrupt output 1 test - vddx i pd - factory test mode select ? must be tied to logic low in application 42 dbg2 clk_s0 vddx i/o dc/pd - debug strobe point / output clock select 46 dbg3 clk_s1 vddx i/o dc/pd - debug strobe point / output clock select oscillator 24 extal clk_cc vddosc i - - crystal driver / external clock 25 xtal - - i - - crystal driver supply/bypass filter pins 8 vddx1 - - - - - supply voltage, i/o table 2-3. pin functions and signal properties (continued) pin # pin name 1 powered by i/o pin type 2, 3 reset functional description function 1 function 2 device overview mfr4300 data sheet, rev. 3 38 freescale semiconductor 37 vddx2 - - - - - supply voltage, i/o 54 vddx3 - - - - - supply voltage, i/o 35 vddx4 - - - - - supply voltage, i/o 9 vssx1 - - - - - supply voltage ground, i/o 38 vssx2 - - - - - supply voltage ground, i/o 53 vssx3 - - - - - supply voltage ground, i/o 31 vssx4 - - - - - supply voltage ground, i/o 20 vddr - - - - - supply voltage, supply to pin drivers and internal voltage regulator 19 vssr - - - - - supply voltage ground, ground to pin drivers and internal voltage regulator 50 vdda - - - - - supply analog voltage 49 vssa - - - - - supply analog voltage ground 59 vdd2_5 4 - - - - - core voltage power supp ly output (nominally 2.5v) 60 vss2_5 4 - - - - - core voltage ground output 26 vddosc 4 - - - - - oscillator voltage power supp ly output (nominally 2.5v) 23 vssosc 4 - - - - - oscillator voltage ground output 1 # ? signal is active-low 2 acronyms: pc ? (pullup/pulldown controlled) register controlled internal weak pullup/pulldown for a pin in the input mode. refer to the following sections for more information: ? section 4.3.1.5, ?host interface pins pullup/pulldown enable register (hipper) ? ? section 4.3.1.6, ?host interface pins pu llup/pulldown control register (hippcr) ? ? section 4.3.1.7, ?physical layer pins pullup/pulldown enable register (plpper) ? ? section 4.3.1.8, ?physical layer pins pullup/pulldown control register (plppcr) ? pd ? (pulldown) internal weak pulldown for a pin in the input mode dc ? (drive strength controlled) register controlled drive streng th for a pin in the output mode. refer to the following sectio ns for more information: ? section 4.3.1.3, ?host interface pins drive strength register (hipdsr) ? ? section 4.3.1.4, ?physica l layer pins drive strength register (plpdsr) ? z ? tristated pin od ? (open drain) output pin with open drain 3 reset state: all pins with the pc option ? pullup/pulldown is disabled, all pins with the dc option ? have full drive strength 4 no load allowed except for bypass capacitors. table 2-3. pin functions and signal properties (continued) pin # pin name 1 powered by i/o pin type 2, 3 reset functional description function 1 function 2 device overview mfr4300 data sheet, rev. 3 freescale semiconductor 39 2.4.3 detailed signal descriptions 2.4.3.1 a[6:1]/xaddr[14:19] ? ami address bus, hcs12 expanded address inputs a[6:1]/xaddr[14:19] are general purpos e input pins. their function is se lected by the if_sel[1:0] pins. refer to section 2.7, ?externa l host interface ? for more information. the pins can be configured to enable or disable either pullup or pull down resistors on the pins. (see section 4.3.1.5, ?host interface pins pullup/pulldown enable register (hipper) ? and section 4.3.1.6, ?host interfac e pins pullup/pulldown control register (hippcr) ?.) a[6:1] are ami interface address signals. a1 is the lsb of the ami address bus. xaddr[14:19] are hcs12 interface expanded addres s lines. xaddr14 is the lsb of the hcs12 interface expanded address lines. 2.4.3.2 a[9:7] ? ami address bus a[9:7] are general purpose input pi ns. their function is selected by the if_sel[1:0] pins. refer to section 2.7, ?external host interface ? for more information. the pins can be configured to enable or disable either pullup or pul ldown resistors on the pins. a[9:7] are ami interface address signals. 2.4.3.3 oe#/acs0 ? ami read output enable, hcs12 address select input oe#/acs0 is a general purpose input pin. its function is selected by the if_sel[1:0] pins. refer to section 2.7, ?external host interface ? for more information. the pin can be configured to enable or disable either a pullup or pulldown resistor on the pin. oe# is the ami interface output enable signal. this signal controls mfr4300 data output and the state of three-stated data pins d[15: 0] during host read operations. acs0 is an hcs12 interface address select signal. 2.4.3.4 a[12:11]/acs[2:1] ? ami address bus, hcs12 expa nded address inputs a[12:11]/acs[2:1] are general purpos e input pins. their function is se lected by the if_sel[1:0] pins. refer to section 2.7, ?externa l host interface ? for more information. the pins can be configured to enable or disable either pullup or pul ldown resistors on the pins. a[12:11] are ami interface address signals. acs[1:2] are hcs12 interfac e address select signals. 2.4.3.5 bsel[1:0]#/dbg[0:1] ? ami by te select, debug strobe points bsel[1:0]#/dbg[0:1] are general purpose input or output pins. th eir function is selected by the if_sel[1:0] pins. refer to section 2.7, ?external host interface ? for more information. the pins can be device overview mfr4300 data sheet, rev. 3 40 freescale semiconductor configured to provide either high or reduced output dr ive, and also to enable or disable either pullup or pulldown resistors on the pins. bsel[1:0]# are ami byte select signals. dbg[0:1] are debug strobe point out put signals. the functions output on these pins are selected by the debug port control register. refer to section 3.4.16, ?strobe signal support? for more information. 2.4.3.6 d[15:8]/pb[0:7] ? ami data bus, hcs12 multiplexed address/data bus d[15:8]/pb[0:7] are general purpose i nput or output pins. their functions are selected by the if_sel[1:0] pins. refer to section 2.7, ?externa l host interface ? for more information. thes e pins can be configured to provide either high or reduced output drive, and al so to enable or disable either pullup or pulldown resistors on the pins. d[15:8] are data signals of the ami interf ace. d15 is the msb of the ami data bus. pb[0:7] are hcs12 interface multiplexed address/data signals in the hcs12 host interface mode of operation. pb0 is the lsb of the hcs12 address/data bus. 2.4.3.7 d[7:0]/pa[0:7] ? ami data bus, hcs12 multiplexed address/data bus d[7:0]/pa[0:7] are general purpose i nput or output pins. their functions are selected by the if_sel[1:0] pins. refer to section 2.7, ?externa l host interface ? for more information. thes e pins can be configured to provide either high or reduced output drive, and al so to enable or disable either pullup or pulldown resistors on the pins. d[7:0] are data signals of the ami interf ace. d0 is the lsb of the ami data bus. pa[0:7] are hcs12 interface multip lexed address/data signals in th e hcs12 host interface mode of operation. pa7 is the msb of the hcs12 address/data bus. 2.4.3.8 ce#/lstrb ? ami chip se lect, hcs12 low-byte strobe the function of this pin is sele cted by if_sel[1:0] pins. refer section 2.7, ?external host interface ? for more information. the pin can be configured to enab le or disable either a pu llup or pulldown resistor on the pin. ce# is an ami interface transfer size in put signal. it indicates the size of the requested data transfer in the current bus cycle. lstrb is an hcs12 interface low-byte strobe input signal. it indicates the type of bus access. 2.4.3.9 we#/rw_cc# ? ami write enable, hcs12 read/write select the function of this pin is selected by the if_sel[1:0] pins. refer to section 2.7, ?external host interface ? for more information. the pin can be configured to enable or di sable either a pullup or pulldown resistor on the pin. we# is an ami interface writ e select signal. it strobes the valid data provided by the host on the d[15:0] pins during write operations to the mfr4300 memory. device overview mfr4300 data sheet, rev. 3 freescale semiconductor 41 rw_cc# is an hcs12 interface read/write input signal. it indicates the directi on of data transfer for a transaction. 2.4.3.10 a10/eclk_cc ? ami address bus, hcs12 clock input the function of this pin is select ed by the if_sel[1:0] pins. refer section 2.7, ?external host interface ? for more information. the pi n can be configured to enable or disabl e either a pullup or pulldown resistor on the pin. a10 is an ami interface address signal. eclk_cc is the hcs12 interface clock input signal. (the maximum frequency of this signal can be calculated from the eclk pulse width low and high times, t lec and t hec given in table a-14 .) 2.4.3.11 rxd_bg[2:1] ? phy data receiver inputs rxd_bg[2:1] are bus driver receive data input signals if the flexray optical/electrical phy is configured: ? rxd_bg1 is the input to the cc from physical layer channel 1 ? rxd_bg2 is the input to the cc from physical layer channel 2 these pins can be configured to enable or disa ble either pullup or pull down resistors on the pins. 2.4.3.12 txen[2:1]# ? phy transmit enable txen[2:1]# are bus driver transm it enable output signals if the fl exray optical/electrical phy is configured: ? txen1# is the output of the cc to physical layer channel 1 ? txen2# is the output of the cc to physical layer channel 2 these pins can be configured to provi de either high or reduced output drive. 2.4.3.13 txd_bg[1:2]/if_sel[1:0] ? phy tr ansmit data output s, host interface selection these pins can be configured to provi de either high or reduced output drive. txd_bg[1:2] are bus driver transmit data output si gnals if the flexray optical/electrical phy is configured: ? txd_bg1 is the output of the cc to physical layer channel 1 ? txd_bg2 is the output of the cc to physical layer channel 2 if_sel[1:0] are the cc external interf ace selection input signals. refer to table 2-6 for the selection coding. note the if_sel[1:0] signals are inputs dur ing the internal reset sequence and are latched during the internal reset sequence. device overview mfr4300 data sheet, rev. 3 42 freescale semiconductor while the if_sel[1:0] levels are bei ng latched, the output drive control is disabled, and the internal pulldown re sistors are connect ed to the pins. as if_sel[1:0] signals sh are pins with physical layer interface signals, pullup/pulldown devices must be us ed for the selection. recommended pullup/pulldown resistor values for the if_sel[1:0] inputs are given in section 2.6.3, ?recommended pullup/pulldown resistor values ?. 2.4.3.14 chiclk_cc ? external chi clock input chiclk_cc is the selectable external chi clock i nput. it can be selected to drive the asynchronous memory interface (see section 2.6.2, ?external host interface selection ?). 2.4.3.15 clkout ? clock output clkout is a continuous clock output signal. the frequency of clkout is selected by the clk_s[1:0] pins. the clkout signal, if enabled, is always active: 1. after power-up of the cc, 2. after a low-voltage reset, 3. after a clock monitor failure reset, 4. during and after an external hard reset. the pin can be configured to provide either high or reduced output drive. note as the clkout signal can be disabled during internal resets, refer to section 6.4.3, ?clkout mode selection and control ? for more information on clkout generation dur ing external hard and internal resets. 2.4.3.16 reset# ? external reset reset# is an active-low control signal that acts as an input to initialize the cc to a known startup state. 2.4.3.17 int_cc# ? interrupt output int_cc# is an ami and hcs12 interfaces interrupt request output signal. the cc may request a service routine from the host to run. the interrupt is indicated by the logic level: the inte rrupt is asserted if the int_cc# outputs a logic 0 and is deas serted if int_cc# outputs a logic 1. the pin can be configured to provi de either high or reduced output dr ive. this is an open-drain output. 2.4.3.18 test the test pin is pulled down, internally, and mu st be tied to vss in all applications. device overview mfr4300 data sheet, rev. 3 freescale semiconductor 43 2.4.3.19 dbg[3:2]/clk_s[1:0] ? debug strobe points, output clock select dbg[3:2] are debug strobe point out put signals. the functions output on these pins are selected by the debug port control register. refer to section 3.4.16, ?strobe signal support? for more information. note clk_s[1:0] signals are inputs during the internal reset sequence and are latched during the internal reset sequence. while the clk_s[1:0] leve ls are being latched, the output drive control is disabled, and the internal pulldown re sistors are connect ed to the pins. 2.4.3.20 extal/cc_clk ? crystal driver, external clock pin this pin can act as a crystal driver pin (extal) or as an external cloc k input pin (cc_clk). on reset, the device clock is derived from the i nput frequency on this pin. refer to figure 2-3 for pierce oscillator connections and figure 2-4 for external clock connections. see also chapter 7, ?oscillator (oscv2)? . 2.4.3.21 xtal ? crystal driver pin xtal is a crystal driver pin. refer to figure 2-3 for oscillator connections and figure 2-4 for external clock connections. see also chapter 7, ?oscillator (oscv2)? . figure 2-3. oscillator connections where: ? q = 40 mhz crystal ? rb is in the range 1m ? 10 m ? rs is a lower value, which can be 0 ?c1 = c2 ? see crystal manufacturer?s product specification for recommended values oscillator supply output capacitor c3 = 220 nf mfr4300 xtal extal vddosc vssosc q c2 c1 rb rs vssosc vssosc c3 device overview mfr4300 data sheet, rev. 3 44 freescale semiconductor figure 2-4. external square wave clock generator connection 2.4.4 power supply pins mfr4300 power and ground pins are summarized in table 2-4 and described below. note all vss pins must be connected together in the application. because fast signal tran sitions place high, short- duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as clos e to the mfr4300 as possible. bypass requirements depend on how heavil y the mfr4300 pins are loaded. table 2-4. mfr4300 power and ground connection summary mnemonic pin number nominal voltage description 64-pin lqfp vdd2_5 59 2.5v internal power and ground generated by internal regulator vss2_5 60 0v vddr 20 3.3v external power and ground, supply to supply to pin drivers and internal voltage regulator. vssr 19 0v vddx[1:4] 8, 37, 54, 35 3.3v external power and ground, supply to pin drivers. vssx[1:4] 9, 38, 53, 31 0v vdda 50 3.3v operating voltage and ground for the internal voltage regulator. vssa 49 0v vddosc 26 2.5v provides operati ng voltage and ground for the internal oscillator. this allows the supply voltage to the osci llator to be bypassed independently. internal power and ground generated by internal regulator. vssosc 23 0v mfr4300 xtal extal vddosc vssosc vssosc c3 where: g = 40 mhz cmos-compatible external oscillator (vddosc-level) clkout g not connected (left open) device overview mfr4300 data sheet, rev. 3 freescale semiconductor 45 2.4.4.1 vddx, vssx ? power and ground pins for i/o drivers external power and ground for i/o drivers. 2.4.4.2 vddr, vssr ? power and ground pins for i/o driver s and internal voltage regulator external power and ground for i/o drivers a nd input to the internal voltage regulator. note the vddr pin enables the internal 3.3 v to 2.5 v voltage regulator. if this pin is tied to ground, the internal voltage regulator is turned off. 2.4.4.3 vdd2_5, vss2_5 ? core power pins power is supplied to the mfr4300 core through vd d2_5 and vss2_5. this 2.5 v supply is derived from the internal voltage regulator. no st atic load is allowed on these pins . if vddr is tied to ground, the internal voltage regulator is turned off. note no load is allowed except for bypass capacitors. 2.4.4.4 vdda, vssa ? power supply pins for vreg vdda, vssa are the power supply a nd ground input pins for th e voltage regulator. th ey also provide the reference voltages for the in ternal voltage regulator. 2.4.4.5 vddosc, vssosc ? power supply pins for osc vddosc, vssosc provide operati ng voltage and ground for the oscill ator. this allows the supply voltage to the oscillator to be bypassed independently. this 2.5 v voltage is generated by the internal voltage regulator. note no load is allowed except for bypass capacitors. 2.5 modes of operation refer to section 3.1.6, ?modes of operation? for full descripti ons of the mfr4300 disabled and normal modes of operation. 2.6 external clock and host interface selection 2.6.1 external 4/10/40 mhz output clock a continuous external 4/10/40 mhz output clock signal is provided by the cc on the clkout pin. see section 2.4.3.15, ?clkout ? clock output ? for details of when this signal is active. device overview mfr4300 data sheet, rev. 3 46 freescale semiconductor the output frequency of the clkout si gnal is selected by the clk_s[1:0] input pins, in accordance with table 2-5 : note as the clk_s[1:0] signals are mu ltiplexed with dbg[2:3], clkout should be selected using pullup and pulldown resistors 2.6.2 external host interface selection the mfr4300 can be connected and controlled by two types of interface through the cc ebi. two pins, if_sel0 and if_sel1, are used to configur e the interface type, in accordance with table 2-6 . the cc latches the values of the if_s el0 and if_sel1 signals, wh en it leaves an internal or external reset state, and analyzes them in order to configure the interface for the type of external host. the cc does not analyze them after it has le ft the reset state. for more information on the internal and ex ternal reset states, see chapter 6, ?clocks and reset generator (crg) ?. note if the cc senses the reserved mode on its if_sel pins (if_sel[1:0] = 00), it stops all internal operations, doe s not perform or respond to any host transactions, stays in the configuratio n mode, and does not integrate into the communication process. the following steps must be taken to se lect a correct external host interface mode: 1.set if_sel0, if_sel1 for either the ami or the hcs12 synchronous mode. table 2-5. clkout frequency selection pin clkout function clk_s0 clk_s1 0 0 4 mhz output 1 0 10 mhz output 0 1 40 mhz output 1 1 disabled (clkout output is ?0?) table 2-6. interface selection pin interface chi and host interface clock if_sel0 if_sel1 0 0 reserved clk_cc 0 1 hcs12 synchronous interface clk_cc 1 0 asynchronous memory interface clk_cc 1 1 asynchronous memory interface chiclk_cc device overview mfr4300 data sheet, rev. 3 freescale semiconductor 47 2.assert the external hard reset signal of the cc again. 2.6.3 recommended pullup/pulldown resistor values as the if_sel[1:0] signals share pins with physical layer interface signals, pul lup and pulldown resistors should be used for the selection. the recommended pullup/pulldown resi stor values for the if_sel[1:0] inputs are given in table 2-7 : 2.7 external host interface the mfr4300 can be connected through two types of bus interface (see section 2.6.2, ?external host interface selection ? for information on how to se lect the host interface). the two types of microprocessor interface are described below. 2.7.1 asynchronous memory interface figure 2-5 shows how to connect the flexray cc to a microcontroller using the ami interface. ? data exchange in ami mode is cont rolled by the ce#, we# and oe# signals. ? the flexray ami interface is implemented as an asynchronous memory slave module, thus enabling fast interfacing between the cc and a variety of microcontrollers. ? the flexray cc mcu interface decodes its internal register addresses with the help of the chip select signal ce# and th e address lines a[12:1]. ? the ami interface accepts only a ligned 16-bit read and 8-bit or 16- bit write transactions. the ami interface does not support 8-bit read accesses. ? the byte selects bsel[1:0]#, the chip enable ce#, the output enab le oe#, and the write enable we# are used to determine the type of access as shown in table 2-8 . table 2-7. recommended pullup and pulldown resistor values for if_sel[1:0] inputs io, regulator and analog supply level ( v dd5 ) pullup resistor 1 1 the listed values are calculated for the mfr4300-physical layer connection where no internal pullup/pulldown resistors are assumed in the electrical phy at the tx d_bg1 and txd_bg2 interface lines. if an electrical phy device has internal pullup/pulldown resistors connected to these signals, then the external pullup/pulldown resistor values must be recalculated to ensure that v il requirements for pulldown resistors or v ih requirements for pullup resistors for the chosen v dd5 are met. see section a.1.9, ?i/o characteristics ? for more details on v il , v ih and v dd5 . pulldown resistor 1 units 3.3v 16 47 k 5v 10 47 k device overview mfr4300 data sheet, rev. 3 48 freescale semiconductor ? we# indicates the direction of data transfer for a transaction. ? oe# enables the ami data output to a microcontroller during read transactions. ? int_cc# is an interrupt line that can be used for requesting, by means of the internal interrupt controller, a service routine from a host controller. ? the flexray cc ami module does not support burst transactions. note for the ami, d0 is the lsb of the 16-bit data bus. note if the ami mode without the chic lk_cc signal is selected (i.e. if_sel[1:0] = 0b01), chiclk_c c must be driven to logic 0 or logic 1 (it must not be left floating). table 2-8. ami access types ce# we# oe# bsel1# bsel0# type of access 0 0 0 x x illegal 0 0 1 0 0 16-bit write to word address 1 1 write data from d[15:8] to even byte addr ess and from d[7:0] to odd byte address. 0 0 1 0 1 8-bit write to even byte address 2 2 write data from d[15:8]. 0 0 1 1 0 8-bit write to odd byte address 3 3 write data from d[7:0]. 0 0 1 1 1 illegal 0 1 1 x x no access 0 1 0 x x 16-bit read from word address 4 4 read data from even byte address at d[15 :8] and from odd byte address at d[7:0]. 1 x x x x no access device overview mfr4300 data sheet, rev. 3 freescale semiconductor 49 2.7.1.1 asynchronous memory interface with mpc5xx and mpc55xx families figure 2-5. ami interface with mpc5xx and mpc55xx families mfr4300 mpc5xx family d0 data0 d15 data15 a1 addr19 a12 addr30 ? ? ? ? we# ce# oe# we# csn# oe# int_cc# txd_bg2/if_sel0 txd_bg1/if_sel1 irqn# vddxn vssxn pl interface be0 be1 bsel1# bsel0# mpc55xx family device overview mfr4300 data sheet, rev. 3 50 freescale semiconductor 2.7.1.2 asynchronous memory interface with s12x family figure 2-6. ami interface with s12x family mfr4300 s12x family d0 d15 d15 d0 a1 a12 a12 a1 ? ? ? ? ce# we# oe# csn we re bsel1# uds lds bsel0# int_cc# txd_bg2/if_sel0 txd_bg1/if_sel1 irqn vddxn pl interface vssxn device overview mfr4300 data sheet, rev. 3 freescale semiconductor 51 2.7.1.3 asynchronous memory interface with dsp 56f83 (hawk) family figure 2-7. ami interface with dsp 56f83 (hawk) family 2.7.1.4 asynchronous memory interface timing see section a.4, ?asynchronous me mory interface timing ? for timing characteristics of the cc ami interface. 2.7.2 hcs12 interface chip selection for the hcs12 inte rface is generated internally us ing the following signals (see figure 2-8 ): ? the input values of the expanded address signa ls xaddr[14:19] are compared with logical 0?s (the hcs12 external bus interface (ebi ) is in the paged or unpaged mode). ? the three most significant bits of the demultip lexed address bus, pa[5:7], are compared with the pattern set up externally on the address chip sel ect pins acs[0:2]; pa5 is compared with acs0, pa6 with acs1, pa7 with acs2. note the address decoding phase of a read/w rite operation is passed if all the comparisons described above are passed. mfr4300 dsp56f83xx family d0 d15 d15 d0 a1 a11 a12 a0 ? ? ? ? we# ce# oe# wr# csn# rd# int_cc# txd_bg2/if_sel0 txd_bg1/if_sel1 irqn# vddxn pl interface vssxn bsel1# bsel0# device overview mfr4300 data sheet, rev. 3 52 freescale semiconductor figure 2-9 shows how to connect the flexray cc to an hcs12 mcu with ebi paged mode support. figure 2-10 shows how to connect he flexray cc to an hcs12 mcu with ebi unpaged mode support. ? the cc?s hcs12 interface supports the paged and the unpaged modes of th e hcs12 external bus interface connected to it. ? the flexray hcs12 interface is implemented as an synchronous hcs12 external bus slave module, thus enabling the fast data exchange between them. ? the flexray cc mcu interface decodes the addresse s of read/write transactions to its internal registers, and generates its internal chip select signal, cs, using the addr ess/data lines pa[0:7], pb[0:7], acs[0:2], and xaddr[14:19]: ? the address and data lines pa[0:7], pb[0:7 ] are multiplexed. they are denoted adr[0:15] when referring to the address, and data[0:15] when referring to the data. the flexray cc is selected only when the address adr[13:15] matches acs[0:2] (adr13 matches acs0, adr12 matches acs1, etc.) and the a ddress xaddr[14: 19] matches 0. ? the hcs12 interface accepts only aligned 16-bit re ad and 8-bit or 16-bit write transactions. the hcs12 interface does not s upport 8-bit read accesses. ? the internal chip select, cs, th e low byte strobe, lstrb, the leas t significant bit of the address, adr0, and the read/write select, rw, are used to determine the type of access, as shown in table 2-9 . ? rw_cc# indicates the direction of data transfer for a transaction. ? int_cc# is an interrupt line that can be used for requesting, by means of the internal interrupt controller, a service routine from the hcs12 device. table 2-9. hcs12 access types cs rw lstrb adr0 type of access 0 x x x no access 1 0 0 0 16-bit write to word address 1 1 write data from pa to even byte address and from pb to odd byte address. 1 0 0 1 8-bit write to an odd address 2 2 write data from pb. 1 0 1 0 8-bit write to an even address 2 1 0 1 1 not supported 1 1 0 0 16-bit read from an even address 3 3 read data from even byte address at pa and from odd byte address at pb. 1 1 0 1 not supported 1 1 1 0 not supported 1 1 1 1 not supported device overview mfr4300 data sheet, rev. 3 freescale semiconductor 53 note ami-only inputs a[9:7], bsel[1:0]#/d bg[0:1] (if the debug strobes are disabled), and chiclk_cc are not used when the hcs12 interface is selected and must be driven to logic 0 or logic 1 (i.e . they must not be left floating). figure 2-8. hcs12 interface address decoding and internal chip select generation 16 bit address /data delimit- plexer 16 bit 16 bit 10 bit 3 bit 3 bit 6 bit 6 bit 2 bit 2 bit & 1 0 1 ?000000? ?01? data[0:15] data signals adr[0:15] address signals adr[0:9] address signals cs pa [ 0 : 7 ] acs[0:2] xaddr[14:19] acs[0:2] xaddr[14:19] adr[14:15] adr[13:15] address comparator 1 address comparator 2 address comparator 3 pb[0:7] device overview mfr4300 data sheet, rev. 3 54 freescale semiconductor 2.7.2.1 hcs12 interface with hcs12 page mode support figure 2-9. hcs12 interface with hcs12 page mode support mfr4300 hcs12 family pb0 pa7 addr/data0 (pb0) ? ? eclk_cc lstrb rw_cc# eclk lstrb r/w# int_cc# txd_bg2/if_sel0 txd_bg1/if_sel1 irqn# vddxn pl interface addr/data15 (pa7) vssxn xaddr19 xaddr14 ? xaddr19 xaddr14 ? acs2 acs1 acs0 device overview mfr4300 data sheet, rev. 3 freescale semiconductor 55 2.7.2.2 hcs12 interface with hcs12 unpaged mode support figure 2-10. hcs12 interface with hcs12 unpaged mode support 2.7.2.3 hcs12 interface timing see section a.5, ?hcs12 interface timing ? for timing characteristics of the hcs12 interface. 2.8 resets and interrupts 2.8.1 resets mfr4300 has the following resets: ? external hard reset input signal reset#. mfr4300 hcs12 family pb0 pa7 addr/data0 (pb0) ? ? eclk_cc lstrb rw_cc# eclk lstrb r/w# int_cc# txd_bg2/if_sel0 txd_bg1/if_sel1 irqn# vddxn pl interface addr/data15 (pa7) vssxn xaddr19 xaddr14 ? acs2 acs1 acs0 vssxn 6 device overview mfr4300 data sheet, rev. 3 56 freescale semiconductor ? internal power-on and low-voltage resets provide d by the internal voltage regulator (refer to chapter 6, ?clocks and reset generator (crg) ? and chapter 5, ?dual output voltage regulator (vreg3v3v2)? for more information). ? internal clock monito r failure reset (see chapter 7, ?oscillator (oscv2)? ). when a reset occurs, mfr4300 register s and control bits are changed to known startup states . refer to the respective module chapters for information on the differ ent kinds of resets and fo r register reset states. 2.8.1.1 i/o pin states after reset refer to table 2-3 for the configuration of th e mfr4300 pins out of reset. 2.8.2 interrupt sources all possible mfr4300 internal interrupt sources are combined and provided to the host by means of one available interrupt line, int_cc#. refer to section 3.4.19, ?interrupt support? and section 6.3.2, ?clock and reset status register (crsr) ? for more information on available interrupt sources. the type of interrupt is level sensitive. mfr4300 data sheet, rev. 3 freescale semiconductor 57 chapter 3 flexray module (flexrayv2) 3.1 introduction 3.1.1 reference the following documents are referenced. ? flexray communications system protocol specification, version 2.1 ? flexray communications system electric al physical layer specification, version 2.1 3.1.2 glossary this section provides a list of terms used in the description of the flexray module. table 3-1. list of terms (sheet 1 of 2) term definition bcu buffer control unit. handles message buffer access. cc communication controller cdc clock domain crosser chi controller host interface cycle length in t the actual length of a cycle in t for the ideal controller (+/- 0 ppm) ebi external bus interface frm flexray memory. memory to store message bu ffer payload, header, and status, and to store synchronization frame related tables. fss frame start sequence hif host interface. provides host access to flexray module. host the flexray cc host mcu lut look up table. stores message buffer header index value. mb message buffer mbidx message buffer index: the position of a header field entry within the header area. if the header area is accessed as an array, this is the same as the array index of the entry. mbnum message buffer number: position of message buff er configuration registers within the register map. for example, message buffer number 5 corresponds to the mbccs5 register. mcu microcontroller unit tmicrotick mt macrotick mts media access test symbol flexray module (flexrayv2) mfr4300 data sheet, rev. 3 58 freescale semiconductor 3.1.3 color coding throughout this chapter types of items are highlight ed through the use of an italicized color font. flexray protocol parameters, constant s and variables are highlighted with blue italics . an example is the parameter gdactionpointoffset . flexray protocol states are highlighted in green italics . an example is the state poc:normal active . 3.1.4 overview the flexray module is a flexray communi cation controller that implements the flexray communications system protoc ol specification, version 2.1. the flexray module has three main components: ? controller host interface (chi) ? protocol engine (pe) ? clock domain crossing unit (cdc) a block diagram of the flexray module w ith its surrounding modules is given in figure 3-1 . nit network idle time pe protocol engine poc protocol operation control. each state of the poc is denoted by poc:state rx reception seq sequencer engine tcu time control unit tx transmission table 3-1. list of terms (sheet 2 of 2) term definition flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 59 figure 3-1. flexray module block diagram the protocol engine has two tran smitter units txa and txb and two receiver units rxa and rxb for sending and receiving frames thr ough the two flexray channels. the time control unit (tcu) is responsible for maintaini ng global clock synchronization to the fl exray network. the overall activity of the pe is controlled by the sequencer engine (seq). the controller host interface provi des host access to the module?s c onfiguration, control, and status registers, as well as to the message buffer configuration, control, and st atus registers. the message buffers themselves, which contain the frame h eader and payload data received or to be transmitted, and the slot status information, are stored in the flexray memory (frm). the clock domain crossing unit implements si gnal crossing from the chi clock domain to the pe clock domain and vice versa, to allow for asynchronous pe and chi clock domains. the flexray module stores the frame header and payl oad data of frames receive d or of frames to be transmitted in the frm. the application accesses the frm to retrieve and provide the frames to be processed by the flexray module. in addition to the frame header and payload data, the flexray module stores the synchronization frame related tabl es in the frm for application processing. note the flexray module does not provide a memory protection scheme for the flexray memory. 3.1.5 features the flexray module provides the following features: clock domain crossing pe txa rxa tcu config seq chi hif search lut bcu rxd_bg1 rxd_bg2 dbg0 txd_bg1 txen1# txd_bg2 txen2# dbg1 dbg2 dbg3 flexray module ebi flexray memory mif flexray module (flexrayv2) mfr4300 data sheet, rev. 3 60 freescale semiconductor ? flexray communications system pr otocol specification, version 2.1 compliant protocol implementation ? flexray communications system electrical physical layer specification, version 2.1 compliant bus driver interface ? single channel support ? internal channel a and flexray port a can be c onfigured to be connected either to physical flexray channel a or physical flexray channel b. ? 128 configurable message buffers with ? individual frame id filtering ? individual channel id filtering ? individual cycle counter filtering ? message buffer header, status and payload data stored in dedicated flexray memory ? allows for flexible and efficient message buffer implementation ? consistent data access ensured by means of buffer locking scheme ? application can lock multiple buffers at the same time ? size of message buffer payload data se ction configurable from 0 up to 254 bytes ? two independent message buffer segments with configurable size of payload data section ? each segment can contain message buffers assigned to the stat ic segment and message buffers assigned to the dynamic segment at the same time ? zero padding for transmit messa ge buffers in static segment ? applied when the frame payloa d length exceeds the size of th e message buffer data section ? transmit message buffers configurable with state/event semantics ? message buffers can be configured as ? receive message buffer ? single buffered transmit message buffer ? double buffered transmit message buffer (com bines two single buffered message buffer) ? individual message buffer r econfiguration supported ? means provided to safely disa ble individual message buffers ? disabled message buffers can be reconfigured ? two independent receive fifos ? one receive fifo per channel ? up to 255 entries for each fifo ? global frame id filtering, based on both value/mask filter s and range filters ? global channel id filtering ? global message id filtering for the dynamic segment ? 4 configurable slot error counters ? 4 dedicated slot status indicators ? used to observe slots without using receive message buffers ? measured value indicators for the clock synchronization flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 61 ? internal synchronizatio n frame id and synchronization fr ame measurement tables can be copied into the flexray memory ? fractional macroticks are supported for clock correction ? maskable interrupt sources provided via individual and combined interrupt lines ? 1 absolute timer ? 1 timer that can be configured to absolute or relative 3.1.6 modes of operation 3.1.6.1 disabled mode this is the default mode the flexra y module enters during hard reset. the flexray module indicates that it is in the disabled m ode by negating the flexray m odule enable bit men in the module configuration register (mcr) . the protocol engine is in its reset state. no communication is performed on the flexray bus. all registers with the write access c onditions any time and disabled mode can be accessed for writing as stated in section 3.3.2, ?register descriptions? . the application can configure the flexray module by accessing the flexray m odule configuration bits and fields in the module configurati on register (mcr) . the flexray module leaves disabled mode when the application sets the flexray module enable bit men in the module configurati on register (mcr) the flexray module then deasse rts the protocol engine reset and puts the protocol engine into the poc:default config state. note after the application has enabled the flexray modul e it cannot disable the flexray module later on. 3.1.6.2 normal mode in this mode the flexray module is fully functional. the flexray module indicates that it is in normal m ode by asserting the flexra y module enable bit (men) in the module configuration register (mcr) . this mode is entered when the appl ication requests the flexray module to leave the disabled mode. if this mode is entered, the prot ocol engine is in its poc:default config state. depending on the values of the sc m, cha, and chb bits in the module configurati on register (mcr) , the corresponding flexray bus driver ports are enabled and driven. the application can tran sition the protocol engine into other protocol states using the protocol operation control register (pocr) . for details regarding protocol states, see flexray communications system protocol specification, version 2.1 . flexray module (flexrayv2) mfr4300 data sheet, rev. 3 62 freescale semiconductor 3.2 external signal description this section lists and desc ribes the flexray module signals, connected to external pins. these signals are summarized in table 3-2 and described in detail in section 3.2.1, ?detailed signal descriptions? . note the off chip signals rxd_bg1, txd_bg1, and txen1# are available on each package option. the availability of the other off chip signals depends on the package option. 3.2.1 detailed signal descriptions this section provides a detailed de scription of the flexray module signa ls, connected to external pins. 3.2.1.1 rxd_bg1 ? receive data channel a the rxd_bg1 signal carries the rece ive data for channel a from th e corresponding flexray bus driver. 3.2.1.2 txd_bg1 ? transmit data channel a the txd_bg1 signal carries the transmit data for channel a to the corresponding flexray bus driver. 3.2.1.3 txen1# ? transmit enable channel a the txen1# signal indicates to the fl exray bus driver that the flexray module is attempting to transmit data on channel a. 3.2.1.4 rxd_bg2 ? receive data channel b the rxd_bg2 signal carries the rece ive data for channel b from th e corresponding flexray bus driver. table 3-2. external signal properties name direction active reset function rxd_bg1 input ? ? receive data channel a txd_bg1 output ? 1 transmit data channel a txen1# output low 1 transmit enable channel a rxd_bg2 input ? ? receive data channel b txd_bg2 output ? 1 transmit data channel b txen2# output low 1 transmit enable channel b dbg0 output ? 0 debug strobe signal 0 dbg1 output ? 0 debug strobe signal 1 dbg2 output ? 0 debug strobe signal 2 dbg3 output ? 0 debug strobe signal 3 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 63 3.2.1.5 txd_bg2 ? transmit data channel b the txd_bg2 signal carries the transmit data fo r channel b to the corresponding flexray bus driver 3.2.1.6 txen2# ? transmit enable channel b the txen2# signal indicates to the fl exray bus driver that the flexray module is attempting to transmit data on channel b. 3.2.1.7 dbg3, dbg2, dbg1, dbg0 ? strobe signals these signals provide the selected debug strobe signals. for details on the debug strobe signal selection refer to section 3.4.16, ?strobe signal support? . 3.3 memory map and register description the flexray module occupies 1280 bytes of address space star ting at address 0x0000. 3.3.1 memory map the complete memory map of the flexray module is shown in table 3-3 . table 3-3. flexray memory map (sheet 1 of 4) address register access module configuration and control 0x0000 module version register (mvr) r 0x0002 module configuration register (mcr) r/w 0x0004 reserved r 0x0006 reserved r 0x0008 strobe signal control register (stbscr) r/w 0x000a strobe port control register (stbpcr) r/w 0x000c message buffer data size register (mbdsr) r/w 0x000e message buffer segment size an d utilization register (mbssutr) r/w test registers 0x0010 reserved r 0x0012 reserved r interrupt and error handling 0x0014 protocol operation co ntrol register (pocr) r/w 0x0016 global interrupt flag and enable register (gifer) r/w 0x0018 protocol interrupt flag register 0 (pifr0) r/w 0x001a protocol interrupt flag register 1 (pifr1) r/w 0x001c protocol interrupt enable register 0 (pier0) r/w 0x001e protocol interrupt enable register 1 (pier1) r/w 0x0020 chi error flag register (chierfr) r/w 0x0022 message buffer interrupt vector register (mbivec) r flexray module (flexrayv2) mfr4300 data sheet, rev. 3 64 freescale semiconductor 0x0024 channel a status error counter register (casercr) r 0x0026 channel b status error counter register (cbsercr) r protocol status 0x0028 protocol status register 0 (psr0) r 0x002a protocol status register 1 (psr1) r 0x002c protocol status register 2 (psr2) r 0x002e protocol status register 3 (psr3) r/w 0x0030 macrotick counter register (mtctr) r 0x0032 cycle counter register (cyctr) r 0x0034 slot counter channel a register (sltctar) r 0x0036 slot counter channel b register (sltctbr) r 0x0038 rate correction value register (rtcorvr) r 0x003a offset correction value register (ofcorvr) r 0x003c combined interrupt flag register (cifrr) r 0x003e reserved r sync frame counter and tables 0x0040 sync frame counter register (sfcntr) r 0x0042 sync frame table offset register (sftor) r/w 0x0044 sync frame table configuration, control, status register (sftccsr) r/w sync frame filter 0x0046 sync frame id rejection filter register (sfidrfr) r/w 0x0048 sync frame id acceptance filt er value register (sfidafvr) r/w 0x004a sync frame id acceptance fi lter mask register (sfidafmr) r/w network management vector 0x004c network management vector register 0 (nmvr0) r 0x004e network management vector register 1 (nmvr1) r 0x0050 network management vector register 2 (nmvr2) r 0x0052 network management vector register 3 (nmvr3) r 0x0054 network management vector register 4 (nmvr4) r 0x0056 network management vector register 5 (nmvr5) r 0x0058 network management vector length register (nmvlr) r/w timer configuration 0x005a timer configuration and control register (ticcr) r/w 0x005c timer 1 cycle set register (ti1cysr) r/w 0x005e timer 1 macrotick offse t register (ti1mtor) r/w 0x0060 timer 2 configuration register 0 (ti2cr0) r/w 0x0062 timer 2 configuration register 1 (ti2cr1) r/w slot status configuration 0x0064 slot status selection register (sssr) r/w 0x0066 slot status counter condition register (ssccr) r/w table 3-3. flexray memory map (sheet 2 of 4) address register access flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 65 slot status 0x0068 slot status register 0 (ssr0) r 0x006a slot status register 1 (ssr1) r 0x006c slot status register 2 (ssr2) r 0x006e slot status register 3 (ssr3) r 0x0070 slot status register 4 (ssr4) r 0x0072 slot status register 5 (ssr5) r 0x0074 slot status register 6 (ssr6) r 0x0076 slot status register 7 (ssr7) r 0x0078 slot status counter register 0 (sscr0) r 0x007a slot status counter register 1 (sscr1) r 0x007c slot status counter register 2 (sscr2) r 0x007e slot status counter register 3 (sscr3) r mts generation 0x0080 mts a configuration register (mtsacfr) r/w 0x0082 mts b configuration register (mtsbcfr) r/w shadow buffer configuration 0x0084 receive shadow buffer index register (rsbir) r/w receive fifo ? configuration 0x0086 receive fifo selection register (rfsr) r/w 0x0088 receive fifo start index register (rfsir) r/w 0x008a receive fifo depth and size register (rfdsr) r/w receive fifo - status 0x008c receive fifo a read index register (rfarir) r 0x008e receive fifo b read index register (rfbrir) r receive fifo - filter 0x0090 receive fifo message id acceptance filter value register (rfmidafvr) r/w 0x0092 receive fifo message id acceptance filter mask register (rfmiafmr) r/w 0x0094 receive fifo frame id rejection f ilter value register (rffidrfvr) r/w 0x0096 receive fifo frame id rejection filter mask register (rffidrfmr) r/w 0x0098 receive fifo range filter configuration register (rfrfcfr) r/w 0x009a receive fifo range filter control register (rfrfctr) r/w dynamic segment status 0x009c last dynamic transmit slot channel a register (ldtxslar) r 0x009e last dynamic transmit slot channel b register (ldtxslbr) r protocol configuration 0x00a0 ... 0x00dc protocol configuratio n register 0 (pcr0) ... protocol configuration register 30 (pcr30) r/w ? r/w table 3-3. flexray memory map (sheet 3 of 4) address register access flexray module (flexrayv2) mfr4300 data sheet, rev. 3 66 freescale semiconductor 3.3.2 register descriptions this section provides detailed descriptions of all re gisters in ascending address order, presented as 16-bit wide entities. table 3-4 provides a key for the register figures and register tables. 3.3.2.1 register reset all registers except the message buffer cycle counte r filter registers (mbccfrn) , message buffer frame id registers (mbfidrn) , and message buffer index registers (mbidxrn) are reset to their reset value on system reset. the registers mentioned above are located in physical memory blocks and, thus, they are not affected by reset. for some register fields, additional rese t conditions exist. these additional reset conditions are mentioned in the detailed descri ption of the register. the additional reset conditions are explained in table 3-5 . 0x00de ... 0x00fe reserved r message buffers configuration, control, status 0x0100 message buffer configuration, cont rol, status register 0 (mbccsr0) r/w 0x0102 message buffer cycle counter filter register 0 (mbccfr0) r/w 0x0104 message buffer frame id register 0 (mbfidr0) r/w 0x0106 message buffer index register 0 (mbidxr0) r/w ... ... ... 0x04f8 message buffer configuration, cont rol, status register 127 (mbccsr127) r/w 0x04fa message buffer cycle counter filter register 127 (mbccfr127) r/w 0x04fc message buffer frame id register 127 (mbfidr127) r/w 0x04fe message buffer index register 127 (mbidxr127) r/w table 3-4. register access conventions convention description the shaded field indicates that t he bit or field is not writeable. r* the r* item indicates a reserved bit or field. the flexray module will not change its value. the application must not write any value differen t from the reset value to this bit or field. reset value 0 resets to zero. 1 resets to one. ? not defined after and not affected by reset. table 3-3. flexray memory map (sheet 4 of 4) address register access flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 67 3.3.2.2 register write access this section describes the write access restri ction terms that apply to all registers. 3.3.2.2.1 register write access restriction for each register bit and register fi eld, the write access conditions are sp ecified in the detailed register description. a description of the wr ite access conditions is given in table 3-6 . if, for a specifi c register bit or field, none of the given wr ite access conditions is fulfil led, any write attempt to th is register bit or field is ignored without any notif ication. the values of the bits or fiel ds are not changed. th e condition term [a or b] indicates that the register or field can be written to if at leas t one of the conditions is fulfilled. 3.3.2.2.2 register write access requirements for some of the registers, a 16-b it wide write access is required to ensure correct operation. this write access requirement is stated in the detailed register descri ption for each register affected 3.3.2.2.3 internal register access the following memory mapped registers are us ed to access multiple internal registers. ? strobe signal control register (stbscr) ? slot status selection register (sssr) ? slot status counter co ndition register (ssccr) ? receive shadow buffer index register (rsbir) each of these memory mapped registers provides a se l field and a wmd bit. the sel field is used to select the internal register. the wmd bit controls th e write mode. if the wmd bi t is set to ?0? during the write access, all fields of the intern al register are updated. if the wmd bit set to ?1?, only the sel field is table 3-5. additional register reset conditions condition description protocol run command the register field is reset when the application writes to run command ?0101? to the poccmd field in the protocol operation control register (pocr) . message buffer disable the register field is reset when the application has disabled the message buffer. this happens when the application writes ?1 ? to the message buffer disable trigger bit mbccsrn.edt while the message buffer is enabled (mbccsn.eds = 1) and the flexray module grants the disable to the application by clearing the mbccsrn.eds bit. table 3-6. register write access restrictions condition indication description any time - no write access restriction. disabled mode mcr.men = ?0? write access only w hen the flexray module is in disabled mode. normal mode mcr.men = ?1? write access only when the flexray module is in normal mode. poc:config psr0.protstate = poc:config write access only when the protocol is in the poc:config state. mb_dis mbccsrn.eds = ?0? write access only when the related message buffer is disabled. mb_lck mbccsrn.lcks = ?1? write access only when the related message buffer is locked. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 68 freescale semiconductor changed. all other fields of the inte rnal register remain unc hanged. this allows for r eading back the values of the selected internal regist er in a subsequent read access. 3.3.2.3 module version register (mvr) this register provides the flexra y module version number. the module version number is derived from the chi version number a nd the pe version number. 3.3.2.4 module configuration register (mcr) this register defines the global c onfiguration of the flexray module. 0x0000 1514131211109876543210 r chiver pever w reset0011010100110101 figure 3-2. module version register (mvr) table 3-7. mvr field descriptions field description 15?8 chiver chi version number ? this field provides the version nu mber of the controller host interface. 7?0 pever pe version number ? this field provides the versio n number of the protocol engine. 0x0002 write: men, scm, chb, cha: disabled mode sffe: disabled mode or poc:config 1514131211109876543210 r men 0 scm chb cha sffe 0 r* 000 r* r* 0 w reset0000000000000000 figure 3-3. module configuration register (mcr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 69 table 3-8. mcr field descriptions field description 15 men module enable ? this bit indicates whether or not the flexray module is in the disabled mode. the application requests the flexray module to leave the disabled mode by writing 1 to this bit. before leaving the disabled mode, the application must configure the sc m, chb, cha, tmode values. for details see section 3.1.6, ?modes of operation? . 0 write: ignored, flexray module disable not possible read: flexray module disabled 1 write: enable flexray module read: flexray module enabled note: if the flexray module is enabled it can not be disabled. 13 scm single channel device mode ? this control bit defines the channel device mode of the flexray module as described in section 3.4.10, ?channel device modes? . 0 flexray module works in dual channel device mode 1 flexray module works in single channel device mode 12?11 chb cha channel enable ? protocol related parameter: pchannels the semantic of these contro l bits depends on the channel device mode controlled by the scm bit and is given ta b l e 3 - 9 . 10 sffe synchronization frame filter enable ? this bit controls the filtering for received synchronization frames. for details see section 3.4.15, ?sync frame filtering? . 0 synchronization frame filtering disabled 1 synchronization frame filtering enabled 8 r* reserved ? this bit is reserved. it is read as ?0?. application must not write ?1? to this bit. 4 r* reserved ? this bit is reserved. it is read as ?0?. application must not write ?1? to this bit. 3?1 r* reserved ? this field is reserved. it is read as ?000?. application must not write ?1? to any bit. table 3-9. channel enable mapping (sheet 1 of 2) scm chb cha description dual channel device modes 0 00 ports rxd_bg1, txd_bg1, and txen1# not driven by flexray module ports rxd_bg2, txd_bg2, and txen1# not driven by flexray module pe channel 0 idle pe channel 1 idle 01 ports rxd_bg1, txd_bg1, and txen1# driven by flexray module ports rxd_bg2, txd_bg2, and txen1# not driven by flexray module pe channel 0 active pe channel 1 idle 10 ports rxd_bg1, txd_bg1, and txen1# not driven by flexray module ports rxd_bg2, txd_bg2, and txen1# driven by flexray module pe channel 0 idle pe channel 1 active 11 ports rxd_bg1, txd_bg1, and txen1# driven by flexray module ports rxd_bg2, txd_bg2, and txen1# driven by flexray module pe channel 0 active pe channel 1 active single channel device mode flexray module (flexrayv2) mfr4300 data sheet, rev. 3 70 freescale semiconductor 3.3.2.5 strobe signal control register (stbscr) this register is used to assign the individual protocol timing related st robe signals given in table 3-11 to the external strobe ports. each strobe signal can be as signed to at most one strobe port. each write access to registers overwrites the previ ously written enb and stbpsel values for the signal indicated by sel. if more than one strobe signal is as signed to one strobe port, the curren t values of the strobe signals are combined with a binary or and presented at the strobe port. if no strobe signal is assigned to a strobe port, the strobe port carries logic 0. for more detailed and timing in formation refer to section 3.4.16, ?strobe signal support? . note in single channel device mode, cha nnel b related strobe signals are undefined and should not be as signed to the strobe ports. 1 00 ports rxd_bg1, txd_bg1, and txen1# not driven by flexray module ports rxd_bg2, txd_bg2, and txen1# not driven by flexray module pe channel 0 idle pe channel 1 idle 01 ports rxd_bg1, txd_bg1, and txen1# driven by flexray module ports rxd_bg2, txd_bg2, and txen1# not driven by flexray module pe channel 0 active pe channel 1 idle 10 ports rxd_bg1, txd_bg1, and txen1# driven by flexray module ports rxd_bg2, txd_bg2, and txen1# not driven by flexray module pe channel 0 active, uses ccrcinit[b] (see figure 3-132 ) pe channel 1 idle 11reserved 0x0008 16-bit write access required write: any time 1514131211109876543210 r0 sel 000 enb 00 stbpsel wwmd reset0000000000000000 figure 3-4. strobe signal control register (stbscr) table 3-10. stbscr field descriptions (sheet 1 of 2) field description 15 wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. 14?8 sel strobe signal select ? this control field selects one of the strobe signals given in ta b l e 3 - 1 1 to be enabled or disabled and assigned to one of the four strobe ports given in ta bl e 3 - 1 1 . table 3-9. channel enable mapping (sheet 2 of 2) scm chb cha description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 71 .; 4 enb strobe signal enable ? the control bit is used to enable and to disable the strobe signal selected by stbssel. 0 strobe signal is disabled and not assigned to any strobe port. 1 strobe signal is e nabled and assigne d to the strobe port selected by stbpsel. 1?0 stbpsel strobe port select ? this field selects the strobe port that the strobe signal selected by the sel is assigned to. all strobe signals that are enabled and assigned to the same strobe port are combined with a binary or operation. 00 assign selected signal to dbg0 01 assign selected signal to dbg1 10 assign selected signal to dbg2 11 assign selected signal to dbg3 table 3-11. strobe signal mapping (sheet 1 of 3) sel description channel type offset 1 reference dec hex 0 0x00 poc_startup_state[0] (for coding see psr0[4]) - value 0 mt start 1 0x01 poc_startup_state[1] (for coding see psr0[5]) 2 0x02 poc_startup_state[2] (for coding see psr0[6]) 3 0x03 poc_startup_state[3] (for coding see psr0[7]) 4 0x04 poc_state[0] (for coding see psr0[8]) 5 0x05 poc_state[1] (for coding see psr0[9]) 6 0x06 poc_state[2] (for coding see psr0[10]) 7 0x07 channel idle indicator a level +5 rxd_bg1 8 0x08 b rxd_bg2 9 0x09 receive data after glitch filtering a value +4 rxd_bg1 10 0x0a b rxd_bg2 11 0x0b synchronization edge strobe a pulse +4 rxd_bg1 12 0x0c b rxd_bg2 13 0x0d header received a pulse +4 rxd_bg1 14 0x0e b rxd_bg2 15 0x0f wakeup symbol decoded a pulse +5 rxd_bg1 16 0x10 b rxd_bg2 17 0x11 mts or cas symbol decoded a pulse +4 rxd_bg1 18 0x12 b rxd_bg2 19 0x13 frame decoded a pulse +4 rxd_bg1 20 0x14 b rxd_bg2 21 0x15 channel idle detected a pulse +4 rxd_bg1 22 0x16 b rxd_bg2 23 0x17 start of communication element detected a pulse +4 rxd_bg1 24 0x18 b rxd_bg2 25 0x19 potential frame start channel a pulse +4 rxd_bg1 26 0x1a b rxd_bg2 table 3-10. stbscr field descriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 72 freescale semiconductor 27 0x1b wakeup collision detected a pulse +5 rxd_bg1 28 0x1c b rxd_bg2 29 0x1d content error detected a level +4 rxd_bg1 30 0x1e b rxd_bg2 31 0x1f syntax error detected a pulse +4 rxd_bg1 32 0x20 b rxd_bg2 33 0x21 start transmission of wakeup pattern a pulse -1 txd_bg1 34 0x22 b txd_bg2 35 0x23 start transmission of mts or cas symbol a pulse -1 txd_bg1 36 0x24 b txd_bg2 37 0x25 start of transmission a pulse -1 txd_bg1 38 0x26 b txd_bg2 39 0x27 end of transmission a pulse -1 txd_bg1 40 0x28 b txd_bg2 41 0x29 static segment in dicator - level 0 mt start 42 0x2a dynamic segment indicator - level 0 mt start 43 0x2b symbol window indicator - level 0 mt start 44 0x2c nit indicator - level 0 mt start 45 0x2d action point - pulse -1 txd_bg1 46 0x2e sync calculation complete 2 -pulse- - 47 0x2f start of offset correction - pulse -2 mt start 48 0x30 cycle count[0] - value -2 mt start 49 0x31 cycle count[1] 50 0x32 cycle count[2] 51 0x33 cycle count[3] 52 0x34 cycle count[4] 53 0x35 cycle count[5] 54 0x36 slot count[0] a value 0 mt start 55 0x37 slot count[1] 56 0x38 slot count[2] 57 0x39 slot count[3] 58 0x3a slot count[4] 59 0x3b slot count[5] 60 0x3c slot count[6] 61 0x3d slot count[7] 62 0x3e slot count[8] 63 0x3f slot count[9] 64 0x40 slot count[10] table 3-11. strobe signal mapping (sheet 2 of 3) sel description channel type offset 1 reference dec hex flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 73 3.3.2.6 strobe port control register (stbpcr) this register is used to enable and disable the strobe port sign als. each disabled port wi ll stay disabled even when strobe signals are assigned to it. 65 0x41 slot count[0] b value 0 mt start 66 0x42 slot count[1] 67 0x43 slot count[2] 68 0x44 slot count[3] 69 0x45 slot count[4] 70 0x46 slot count[5] 71 0x47 slot count[6] 72 0x48 slot count[7] 73 0x49 slot count[8] 74 0x4a slot count[9] 75 0x4b slot count[10] 76 0x4c cycle start - pulse 0 mt start 77 0x4d slot start a pulse 0 mt start 78 0x4e b 79 0x4f minislot start - pulse 0 mt start 80 0x50 arm - value +1 mt start 81 0x51 mt - value +1 mt start 1 given in pe clock cycles 2 indicates internal pe event not dire ctly related to flexray bus timing 0x000a write: any time 1514131211109876543210 r000000000000 stb3en stb2en stb1en stb0en w reset0000000000000000 figure 3-5. strobe port control register (stbpcr) table 3-12. stbpcr field descriptions field description 3 stb3en strobe port 3 enable ? this control bit defines whether the dbg3 port is enabled or disabled. 0 strobe port dbg3 disabled 1 strobe port dbg3 enabled 2 stb2en strobe port 2 enable ? this control bit defines whether the dbg2 port is enabled or disabled. 0 strobe port dbg2 disabled 1 strobe port dbg2 enabled table 3-11. strobe signal mapping (sheet 3 of 3) sel description channel type offset 1 reference dec hex flexray module (flexrayv2) mfr4300 data sheet, rev. 3 74 freescale semiconductor 3.3.2.7 message buffer data size register (mbdsr) this register defines the size of the message buffer data section for th e two message buffer segments in a number of two-byte entities. the flexray module provides two independent se gments for the individual message buffers. all individual message buffers within one segment have to have the same size for the message buffer data section. this size can be different for the two message buffer segments. 3.3.2.8 message buffer segment size and utilization register (mbssutr) this register is used to define the last individual message buffer that belongs to the first message buffer segment and the number of the last used individual message buffer. 1 stb1en strobe port 1 enable ? this control bit defines whether the dbg1 port is enabled or disabled. 0 strobe port dbg1 disabled 1 strobe port dbg1 enabled 0 stb0en strobe port 0 enable ? this control bit defines whether the dbg0 port is enabled or disabled. 0 strobe port dbg0 disabled 1 strobe port dbg0 enabled 0x000c write: poc:config 1514131211109876543210 r0 mbseg2ds 0 mbseg1ds w reset0000000000000000 figure 3-6. message buffer data size register (mbdsr) table 3-13. mbdsr field descriptions field description 14?8 mbseg2ds message buffer segment 2 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the second message buffer segment. 6?0 mbseg1ds message buffer segment 1 data size ? the field defines the size of the message buffer data section in two-byte entities for message buffers within the first message buffer segment. 0x000e write: poc:config 1514131211109876543210 r0 last_mb_seg1 0 last_mb_util w reset0111111101111111 figure 3-7. message buffer segment size and utilization register (mbssutr) table 3-12. stbpcr field descriptions (continued) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 75 3.3.2.9 protocol operation control register (pocr) the application uses th is register to issue ? protocol control commands ? external clock correction commands protocol control commands are issu ed by writing to the po ccmd field. for more in formation on protocol control commands, see section 3.6.2, ?protocol cont rol command execution? . external clock correction commands are issued by wr iting to the eoc_ap and erc_ap fields. for more information on external clock correction, refer to section 3.4.11, ?external clock synchronization? . table 3-14. mbssutr field descriptions field description 14?8 last_mb_seg1 last message buffer in segment 1 ? this field defines the message buffer number of the last individual message buffer that is assigned to the first message buffer segment. the individual message buffers in the first segment correspond to the message buffer control registers mbccsrn, mbccfrn, mbfidrn, mbidxrn with n <= last_mb_seg1. the first mess age buffer segment contains last_mb_seg1+1 individual message buffers. note: the first message buffer segment contains at least one individual message buffer. the individual message buffers in the second message buffer segment correspond to the message buffer control registers mbccsrn, mbccfrn, mbfi drn, mbidxrn with last_mb_seg1 < n < 128. note: if last_mb_seg1 = 127 all individual message buffers belong to the first message buffer segment and the second message buffer segment is empty. 6?0 last_mb_util last message buffer utilized ? this field defines the message buff er number of last utilized individual message buffer. the message buffer search engine examines all individual message buffer with a message buffer number n <= last_mb_util. note: if last_mb_util=last_mb_seg1 all individu al message buffers belong to the first message buffer segment and the second message buffer segment is empty. 0x0014 write: normal mode 1514131211109876543210 r0000 0 0 bsy000 poccmd wwme eoc_ap erc_ap wmc reset0000000000000000 figure 3-8. protocol operation control register (pocr) table 3-15. pocr field descriptions (sheet 1 of 2) field description 15 wme write mode external correction ? this bit controls the write mode of the eoc_ap and erc_ap fields. 0 write to eoc_ap and erc_ap fields on register write. 1 no write to eoc_ap and erc_ap fields on register write. 11?10 eoc_ap external offset corr ection application ? this field is used to trigger the application of the external offset correction value defined in the protocol configuration register 29 (pcr29) . 00 do not apply external offset correction value 01 reserved 10 subtract external offset correction value 11 add external offset correction value flexray module (flexrayv2) mfr4300 data sheet, rev. 3 76 freescale semiconductor 9?8 erc_ap external rate correction application ? this field is used to trigger application of the external rate correction value defined in the protocol configuration register 21 (pcr21) 00 do not apply external rate correction value 01 reserved 10 subtract external rate correction value 11 add external rate correction value 7 bsy wmc protocol control command write busy ? this status bit indicates the a cceptance of the protocol control command issued by the application via the poccmd field. the flexray module sets this status bit when the application has issued a protocol co ntrol command via the poccmd fiel d. the flexray module clears this status bit when protocol control command was accept ed by the pe.when the application issues a protocol control command while the bsy bit is asserted, the flexra y module ignores this command, sets the protocol command ignored error flag pcmi_ef in the chi error flag register (chierfr) , and will not change the value of the poccmd field. 0 command write idle, command accepted an d ready to receive new protocol command. 1 command write busy, command not yet accepted, not ready to receive new protocol command. write mode command ? this bit controls the write mode of the poccmd field. 0 write to poccmd field on register write. 1 do not write to poccmd field on register write. 3?0 poccmd protocol control command ? the application writes to this field to issue a protocol control command to the pe. the flexray module sends the protocol command to th e pe immediately. while the transfer is running, the bsy bit is set. 0000 allow_coldstart ? immediately activate capa bility of node to cold start cluster. 0001 all_slots ? delayed 1 transition to the all slots transmission mode. 0010 config ? immediately transition to the poc:config state. 0011 freeze ? immediately transition to the poc:halt state. 0100 ready, config_complete ? i mmediately transition to the poc:ready state. 0101 run ? immediately transition to the poc:startup start state. 0110 default_config ? immediately transition to the poc:default config state. 0111 halt ? delayed transition to the poc:halt state 1000 wakeup ? immediately initiate the wakeup procedure. 1001 reserved 1010 reserved 1011 reserved 1100 reset 2 ? immediately reset the protocol engine. 1101 reserved 1110 reserved 1111 reserved 1 delayed means on completion of current communication cycle. 2 additional to flexray communications system pr otocol specification, version 2.1 note after sending the reset command, it is mandatory to execute the command sequence described in section 3.6.3, ?protocol reset command? immediately, to reach the def ault config state correctly. table 3-15. pocr field descriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 77 3.3.2.10 global interrupt flag and enable register (gifer) this register provides the means to control some of the interrupt request lines and provides the corresponding interrupt flags. the interrupt flags mif, prif, chif, rbif, and tbif are the outcome of a binary or of the related individual interrupt flags and interrupt enable s. the generation scheme for these flags is depicted in figure 3-141 . for more details on interrupt generation, see section 3.4.19, ?interrupt support . these flags are cleared automati cally when all of the correspondi ng interrupt flags or interrupt enables in the related interrupt flag and enable registers are cleared by th e application. in th is register the application can clear only the interr upt flags wupif, fnebif , and fneaif, by writi ng ?1? to each them. writing ?0? will not change the flag state. if the application clears a flag and the flexray module sets the flag on the same cycle, th en that flag remains set. 0x0016 write: normal mode 1514131211109876543210 r mif prif chif wupif fnebif fneaif rbif tbif mie prie chie wupie fnebie fneaie rbie tbie w reset0000000000000000 figure 3-9. global interrupt flag and enable register (gifer) table 3-16. gifer field descriptions (sheet 1 of 3) field description 15 mif module interrupt flag ? this flag is set if at least one of the other interrupt flags is in this register is asserted and the related interrupt enable is asserted, too. the flexray module generates the module interrupt request if mie is asserted. 0 no interrupt flag is asserted or no interrupt enable is set 1 at least one of the other interrupt flags in this register is asserted and the related interrupt bit is asserted, too 13 prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag re gister 0 (pifr0) and protocol interrupt flag register 1 (pifr1) is asserted and the related interrupt enable flag is asserted, too. the flexray module generates the combined protocol interrupt request if the prie flag is asserted. 0 all individual protocol interrupt flags are equ al to 0 or no interrupt enable bit is set. 1 at least one of the individual protocol interrupt flags and the related interrupt enable is equal to 1. 13 chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (chierfr) is asserted and the chi error interrupt e nable gifer.chie is asserted. the flexray module generates the combined chi error inte rrupt if the chie flag is asserted, too. 0 all chi error flags are equal to 0 or the chi error interrupt is disabled 1 at least one chi error flag is asserted and chi error interrupt is enabled 12 wupif wakeup interrupt flag ? this flag is set when the flexray module has received a wakeup symbol on the flexray bus. the application can determine on which channel the wakeup symbol was received by reading the related wakeup flags wub and wua in the protocol status register 3 (psr3). the flexray module generates the wakeup interrupt request if the wupie flag is asserted. 0 no wakeup condition or interrupt disabled 1 wakeup symbol received on flexray bus and interrupt enabled 11 fnebif receive fifo channel b not empty interrupt flag ? this flag is set when the receive fifo for channel b is not empty. if the application writes 1 to this bit, the fl exray module updates the fifo status, increments or wraps the fifo read index in the receive fifo b read index register (rfbrir) and clears the interrupt flag if the fifo b is now empty. if the fifo is still not empty, the flexray module sets this flag again. the flexray module generates the receive fifo b not empty interrupt if the fnebie flag is asserted. 0 receive fifo b is empty or interrupt is disabled 1 receive fifo b is not empty and interrupt enabled flexray module (flexrayv2) mfr4300 data sheet, rev. 3 78 freescale semiconductor 10 fneaif receive fifo channel a not empty interrupt flag ? this flag is set when the receive fifo for channel a is not empty. if the application writes 1 to this bit, the fl exray module updates the fifo status, increments or wraps the fifo read index in the receive fifo a read index register (rfarir) and clears the interrupt flag if the fifo a is now empty. if the fifo is still not empty, the flexray module sets this flag again. the flexray module generates the receive fifo a not empty interrupt if the fneaie flag is asserted. 0 receive fifo a is empty or interrupt is disabled 1 receive fifo a is not empty and interrupt enabled 9 rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (mbccsn.mtd = 0) both the interrupt flag mbif and the interrupt enable bit mbie in the corresponding message buffer configur ation, control, stat us registers (mbccsrn) are asserted. the application can not clear this rbif flag directly. this flag is cleared by the flexray module when all of the interrupt flags mbif of the individual receive message buffers are cleared by the application or if the application has cleared the interrupt enables bit mbie. 0 none of the individual receive message bu ffers has the mbif and mbie flag asserted. 1 at least one individual receive message buffer has the mbif and mbie flag asserted. 8 tbif transmit buffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (mbccsn.mtd = 0) both the interrupt flag mbif and the interrupt enable bit mbie in the corresponding message buffer configuration, cont rol, status registers (mbccsrn) are equal to ?1?. the application can not clear this tbif flag di rectly. this flag is cleared by the flexray module when either all of the individual interrupt flags mbif of the individual transm it message buffers are cleared by the application or the host has cleared the interrupt enables bit mbie. 0 none of the individual transmit message buffers has the mbif and mbie flag asserted. 1 at least one individual transmit message buffer has the mbif and mbie flag asserted. 7 mie module interrupt enable ? this flag controls if the module interr upt line is asserted when the mif flag is set. 0 disable interrupt line 1 enable interrupt line 6 prie protocol interrupt enable ? this flag controls if the protocol interr upt line is asserted when the prif flag is set. 0 disable interrupt line 1 enable interrupt line 5 chie chi interrupt enable ? this flag controls if the chi interrupt line is asserted when the chif flag is set. 0 disable interrupt line 1 enable interrupt line 4 wupie wakeup interrupt enable ? this flag controls if the wakeup inte rrupt line is asserted when the wupif flag is set. 0 disable interrupt line 1 enable interrupt line 3 fnebie receive fifo channel b not empty interrupt enable ? this flag controls if the receive fifo b interrupt line is asserted when the fnebif flag is set. 0 disable interrupt line 1 enable interrupt line 2 fneaie receive fifo channel a not empty interrupt enable ? this flag controls if the receive fifo a interrupt line is asserted when the fneaif flag is set. 0 disable interrupt line 1 enable interrupt line table 3-16. gifer field descriptions (sheet 2 of 3) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 79 3.3.2.11 protocol interrupt flag register 0 (pifr0) the register holds one set of the protocol related i ndividual interrupt flags. the application clears an interrupt flag by writing a '1' to it. wr iting a ?0? will not change the state of the flag. if the application tries to clear a flag and the flexray module sets this flag at the same 13time, then that flag remains set. 1 rbie receive buffer interrupt enable ? this flag controls if the receive buffer interrupt line is asserted when the rbif flag is set. 0 disable interrupt line 1 enable interrupt line 0 tbie transmit interrupt enable ? this flag controls if the transmit buff er interrupt line is asserted when the tbif flag is set. 0 disable interrupt line 1 enable interrupt line 0x0018 write: normal mode 1514131211109876543210 r fatl_if intl_if ilcf_if csa_if mrc_if moc_if ccl_if mxs_if mtx_if ltxb_if ltxa_if tbvb_if tbva_if ti2_if ti1_if cys_if w reset0000000000000000 figure 3-10. protocol interrupt flag register 0 (pifr0) table 3-17. pifr0 field descriptions (sheet 1 of 3) field description 15 fatl_if fatal protocol error interrupt flag ? this flag is set when the protocol engine has detected a fatal protocol error. in this case, the protocol engine goes into the poc:halt state immediately. the fatal protocol errors are: 1) platesttx violation, as described in the mac process of the flexray protocol 2) transmission across slot boundary violation, as described in the fsp process of the flexray protocol 0 no such event. 1 fatal protocol error detected. 14 intl_if internal protocol error interrupt flag ? this flag is set when the protocol engine has detected an internal protocol error. in this case, th e protocol engine goes into the poc:halt state immediately. an internal protocol error occurs when the protocol engine has not finished a calculation and a new calculation is requested. this can be caused by a hardware error. 0 no such event. 1 internal protocol error detected. 13 ilcf_if illegal protocol configuration interrupt flag ? this flag is set when the protocol engine has detected an illegal protocol configuration parameter setting. in this case, the protocol engine goes into the poc:halt state immediately. the protocol engine checks the listen_timeout value programmed into the protocol configuration register 14 (pcr14) and protocol configuratio n register 15 (pcr15) when the config_complete command was sent by the application via the protocol operation control register (pocr) . if the value of listen_timeout is equal to zero, the protocol co nfiguration setting is considered as illegal. 0 no such event. 1 illegal protocol configuration detected. table 3-16. gifer field descriptions (sheet 3 of 3) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 80 freescale semiconductor 12 csa_if cold start abort interrupt flag ? this flag is set when the configured number of allowed cold start attempts is reached and none of these attempts was successful. the nu mber of allowed cold start attempts is configured by the coldstart_attempts field in the protocol configuratio n register 0 (pcr0) . 0 no such event. 1 cold start aborted and no more coldstart attempts allowed. 11 mrc_if missing rate correction interrupt flag ? this flag is set when an insufficient number of measurements is available for rate correction at the end of the communication cycle. 0 no such event 1 insufficient number of measurements for rate correction detected 10 moc_if missing offset corr ection interrupt flag ? this flag is set when an insufficient number of measurements is available for offset correction. this is related to the missing_term event in the csp process for offset correction in the flexray protocol. 0 no such event. 1 insufficient number of measurements for offset correction detected. 9 ccl_if clock correction limit reached interrupt flag ? this flag is set when the internal calculated offset or rate calculation values have reached or exceeded its configured thresholds as given by the offset_coorection_out field in the protocol configuratio n register 9 (pcr9) and the rate_correction_out field in the protocol configuration register 14 (pcr14) . 0 no such event. 1 offset or rate correction limit reached. 8 mxs_if max sync frames detected interrupt flag ? this flag is set when the number of synchronization frames detected in the current communicat ion cycle exceeds the value of the node_sync_max field in the protocol configuration register 30 (pcr30) . 0 no such event. 1 more than node_sync_max sync frames detected. note: only synchronization frames that have passed the syn chronization frame acceptance and rejection filters are taken into account. 7 mtx_if media access test symbol received interrupt flag ? this flag is set when the mts symbol was received on channel a or channel b. 0 no such event. 1 mts symbol received. 6 ltxb_if platesttx violation on channel b interrupt flag ? this flag is set when the frame transmission on channel b in the dynamic segment exceeds the dynamic segment boundary. this is related to the platesttx violation, as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel b. 5 ltxa_if platesttx violation on channel a interrupt flag ? this flag is set when the frame transmission on channel a in the dynamic segment exceeds the dynamic segment boundary. this is related to the platesttx violation as described in the mac process of the flexray protocol. 0 no such event. 1 platesttx violation occurred on channel a. 4 tbvb_if transmission across boundary on channel b interrupt flag ? this flag is set when the frame transmission on channel b crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel b. table 3-17. pifr0 field descriptions (sheet 2 of 3) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 81 3.3.2.12 protocol interrupt flag register 1 (pifr1) the register holds one set of the protocol related i ndividual interrupt flags. the application clears an interrupt flag by writing a ?1? to it. wr iting ?0? will not change the state of the flag. if the application clears a flag while the flexray module sets this flag at the same time, then that flag remains set. 3 tbva_if transmission across boundary on channel a interrupt flag ? this flag is set when the frame transmission on channel a crosses the slot boundary. this is related to the transmission across slot boundary violation as described in the fsp process of the flexray protocol. 0 no such event. 1 transmission across boundary violation occurred on channel a. 2 ti2_if timer 2 expired interrupt flag ? this flag is set whenever timer 2 expires. 0 no such event. 1 timer 2 has reached its time limit. 1 ti1_if timer 1 expired interrupt flag ? this flag is set whenever timer 1 expires. 0 no such event 1 timer 1 has reached its time limit 0 cys_if cycle start interrupt flag ? this flag is set when a communication cycle starts. 0 no such event 1 communication cycle started. 0x001a write: normal mode 1514131211109876543210 r emc_if ipc_if pecf_if psc_if ssi3_if ssi2_if ssi1_if ssi0_if 00 evt_if odt_if 0000 w reset0000000000000000 figure 3-11. protocol interrupt flag register 1 (pifr1) table 3-18. pifr1 field descriptions (sheet 1 of 2) field description 15 emc_if error mode changed interrupt flag ? this flag is set when the value of the errmode bit field in the protocol status register 0 (psr0) is changed by the flexray module. 0 no such event. 1 errmode field changed. 14 ipc_if illegal protocol control command interrupt flag ? this flag is set when the pe tries to execute a protocol control command, which was issued via the poccmd field of the protocol operation control register (pocr) , and detects that this protocol contro l command is not allowed in the current protocol state. in this case the command is not executed. for more details, see section 3.6.2, ?protocol control command execution ?. 0 no such event. 1 illegal protocol control command detected. 13 pecf_if protocol engine communication failure interrupt flag ? this flag is set if the flexray module has detected a communication failure between the protocol engine and the controller host interface 0 no such event. 1 protocol engine communication failure detected. table 3-17. pifr0 field descriptions (sheet 3 of 3) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 82 freescale semiconductor 3.3.2.13 protocol interrupt enable register 0 (pier0) this register defines whether th e interrupt flags defined in the protocol interrupt flag register 0 (pifr0) can generate a interrupt request. 12 psc_if protocol state changed interrupt flag ? this flag is set when the protocol state in the protstate field in the protocol status register 0 (psr0) has changed. 0 no such event. 1 protocol state changed. 11?8 ssi[3:0]_if slot status counter incr emented interrupt flag ? each of these flags is set when the slotstatuscnt field in the corresponding slot status counter registers (sscr0?sscr3) is incremented . 0 no such event. 1 the corresponding slot status counter has incremented. 5 evt_if even cycle table written interrupt flag ? this flag is set if the flexray module has written the sync frame measurement / id tables in to the frm for the even cycle. 0 no such event. 1 sync frame measurement table written 4 odt_if odd cycle table written interrupt flag ? this flag is set if the flexra y module has written the sync frame measurement / id tables in to the frm for the odd cycle. 0 no such event. 1 sync frame measurement table written 0x001c write: any time 1514131211109876543210 r fatl_ie intl_ie ilcf_ie csa_ie mrc_ie moc_ie ccl_ie mxs_ie mtx_ie ltxb_ie ltxa_ie tbvb_ie tbva_ie ti2_ie ti1_ie cys_ie w reset0000000000000000 figure 3-12. protocol interrupt enable register 0 (pier0) table 3-19. pier0 field descriptions field description 15 fatl_ie fatal protocol error interrupt enable ? this bit controls fatl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 14 intl_ie internal protocol error interrupt enable ? this bit controls intl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 13 ilcf_ie illegal protocol configuration interrupt enable ? this bit controls ilcf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 12 csa_ie cold start abort interrupt enable ? this bit controls csa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 11 mrc_ie missing rate correction interrupt enable ? this bit controls mrc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled table 3-18. pifr1 field descriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 83 3.3.2.14 protocol interrupt enable register 1 (pier1) 10 moc_ie missing offset correct ion interrupt enable ? this bit controls moc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 9 ccl_ie clock correction limit reached interrupt enable ? this bit controls ccl_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 8 mxs_ie max sync frames detected interrupt enable ? this bit controls mxs_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 7 mtx_ie media access test symbol received interrupt enable ? this bit controls mt x_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 6 ltxb_ie platesttx violation on channel b interrupt enable ? this bit controls ltxb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 5 ltxa_ie platesttx violation on channel a interrupt enable ? this bit controls ltxa_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 4 tbvb_ie transmission across boundary on channel b interrupt enable ? this bit controls t bvb_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 3 tbva_ie transmission across boundary on channel a interrupt enable ? this bit controls tbva_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 2 ti2_ie timer 2 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 1 ti1_ie timer 1 expired interrupt enable ? this bit controls ti1_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 0 cys_ie cycle start interrupt enable ? this bit controls cyc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 0x001e write: any time 1514131211109876543210 r emc_ie ipc_ie pecf_ie psc_ie ssi3_ie ssi2_ie ssi1_ie ssi0_ie 00 evt_ie odt_ie 0000 w reset0000000000000000 figure 3-13. protocol interrupt enable register 1 (pier1) table 3-19. pier0 field descriptions (continued) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 84 freescale semiconductor this register defines whether the interrupt flags defined in protocol interrupt flag register 1 (pifr1) can generate a interrupt request. 3.3.2.15 chi error flag register (chierfr) this register holds the chi related error flags. the a pplication can clear any erro r flag by writing a '1' to it. writing a ?0? will not change the state of the fla g. if the application clears a flag while the flexray module sets the flag at the same time, then that flag remains set. the interrupt generation for each of these error flags is controlled by the chi interrupt enable bit chie in the global interrupt flag and enable register (gifer) . table 3-20. pier1 field descriptions field description 15 emc_ie error mode changed interrupt enable ? this bit controls emc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 14 ipc_ie illegal protocol control command interrupt enable ? this bit controls ipc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 13 pecf_ie protocol engine communication failure interrupt enable ? this bit controls pecf_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 12 psc_ie protocol state changed interrupt enable ? this bit controls psc_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 11?8 ssi[3:0]_ie slot status counter incr emented interrupt enable ? this bit controls ssi[3:0]_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 5 evt_ie even cycle table written interrupt enable ? this bit controls evt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 4 odt_ie odd cycle table written interrupt enable ? this bit controls odt_if interrupt request generation. 0 interrupt request generation disabled 1 interrupt request generation enabled 0x0020 write: normal mode 1514131211109876543210 r frlb_ef frla_ef pcmi_ef fovb_ef fova_ef mbs_ef mbu_ef lck_ef dbl_ef sbcf_ef fid_ef dpl_ef spl_ef nml_ef nmf_ef ilsa_ef w reset0000000000000000 figure 3-14. chi error fl ag register (chierfr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 85 table 3-21. chierfr field de scriptions (sheet 1 of 2) field description 15 frlb_ef frame lost channel b error flag ? this flag is set if a complete frame was received on channel b but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. in this case, the frame and the related slot status information are lost. 0 no such event 1 frame lost on channel b detected 14 frla_ef frame lost channel a error flag ? this flag is set if a complete frame was received on channel a but could not be stored in the selected individual message buffer because this message buffer is currently locked by the application. in this case, the frame and the related slot status information are lost. 0 no such error 1 frame lost on channel a detected 13 pcmi_ef protocol command ignored error flag ? this flag is set if the application has issued a poc command by writing to the poccmd field in the protocol operation control register (pocr) while the bsy flag is equal to ?1?. in this case the command is ignored by the flexray module and is lost. 0 no such error 1 poc command ignored 12 fovb_ef receive fifo overrun channel b error flag ? this flag is set when an overrun of the receive fifo for channel b occurred. this error occurs if a semantical ly valid frame was received on channel b and matches the all criteria to be appended to the fifo for channel b but the fifo is full. in this case, the received frame and its related slot status information is lost. 0 no such error 1 receive fifo overrun on channel b has been detected 11 fova_ef receive fifo overrun channel a error flag ? this flag is set when an overrun of the receive fifo for channel a occurred. this error occurs if a semantical ly valid frame was received on channel a and matches the all criteria to be appended to the fifo for channel a but the fifo is full. in this case, the received frame and its related slot status information is lost. 0 no such error 1 receive fifo overrun on channel b has been detected 10 msb_ef message buffer search error flag ? this flag is set if the message buffer search engine is still running while the next search cycle must be started due to the flexray protocol timing. in this case, not all message buffers are considered while searching. 0 no such event 1 search engine active while search start appears 9 mbu_ef message buffer utilization error flag ? this flag is asserted if the application writes to a message buffer control field that is beyond the number of utilized message buffers programmed in the message buffer segment size and utilizati on register (mbssutr) . if the application writes to a mbccsrn register with n > last_mb_util, the flexray module ignores the write attempt and asserts the message buffer utilization error flag mbu_ef in the chi error flag register (chierfr) . 0 no such event 1 non-utilized message buffer enabled 8 lck_ef lock error flag ? this flag is set if the application tries to lock a message buffer that is already locked by the flexray module due to internal operations. in that case, the flexray module does not grant the lock to the application. the application must issue the lock request again. 0 no such error 1 lock error detected 7 dbl_ef double transmit message buffer lock error flag ? this flag is set if the application tries to lock the transmit side of a double transmit message buffer. in this case, the flexray module does not grant the lock to the transmit side of a double transmit message buffer. 0 no such event 1 double transmit buffer lock error occurred flexray module (flexrayv2) mfr4300 data sheet, rev. 3 86 freescale semiconductor 3.3.2.16 message buffer interrupt vector register (mbivec) 6 sbcf_ef system bus communication failure error flag ? this flag is set if the flexray module was not able to transmit or receive data via the system bus in time. in the case of writing, data is lost; in the case of reading, the transmission onto the flexray bus is stopped for t he current slot and resumed in the next slot. 0 no such event 1 system bus communication failure occurred 5 fid_ef frame id error flag ? this flag is set if the frame id stored in the message buffer header area differs from the frame id stored in the message buffer control register. 0 no such error occurred 1 frame id error occurred 4 dpl_ef dynamic payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assigned to the dynamic segment is greater than the maximum payload length for the dynamic segment as it is configured in the correspond ing protocol configuration register field max_payload_length_dynamic in the protocol configuration register 24 (pcr24) . 0 no such error occurred 1 dynamic payload length error occurred 3 spl_ef static payload length error flag ? this flag is set if the payload length written into the message buffer header field of a single or double transmit message buffer assig ned to the static segment is different from the payload length for the static segment as it is configured in the corresponding protocol c onfiguration register field payload_length_static in the protocol configuration register 19 (pcr19) . 0 no such error occurred 1 static payload length error occurred 2 nml_ef network management length error flag ? this flag is set if the payload length written into the header structure of a receive message buffer assigned to the st atic segment is less than t he configured length of the network management vector as configured in the network management vector length register (nmvlr) . in this case the received part of the network ma nagement vector will be used to update the network management vector. 0 no such error occurred 1 network management length error occurred 1 nmf_ef network management frame error flag ? this flag is set if a received message in the static segment with a preamble indicator flag pp asserted has its null frame indi cator flag nf asserted as well. in this case, the global network management registers (see network management vector registers (nmvr0?nmvr5) ) are not updated. 0 no such error occurred 1 network management frame error occurred 0 ilsa_ef illegal system memory access error flag ? this flag is set if the exte rnal system memory subsystem has detected and indicated an illegal system memory access from the flexray module. the exact meaning of an illegal system memory access is defined by the current implementation of the memory subsystem. 0 no such event. 1 illegal system memory access occurred. 0x0022 1514131211109876543210 r 0 tbivec 0 rbivec w reset0000000000000000 figure 3-15. message buffer interrupt vector register (mbivec) table 3-21. chierfr field de scriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 87 this register indicates the lowest numbered receive message buffer and the lo west numbered transmit message buffer that have their interr upt status flag mbif and interrupt enable mbie bits asserted. this means that message buffers with lower me ssage buffer numbers have higher priority. 3.3.2.17 channel a status erro r counter register (casercr) this register provides the channel st atus error counter for channel a. th e protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, a nd the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror, vss!cont enterror, vss!bviolation , and vss!txconflict . the flexray module increments the counter by 1 if, for a slot or se gment, at least one error indicator bit is set to ?1?. the counter wraps around after it has r eached the maximum value. for more information on slot status monitoring, see section 3.4.18, ?slot status monitoring ?. 3.3.2.18 channel b status erro r counter register (cbsercr) table 3-22. mbivec field descriptions field description 14-8 tbivec transmit buffer interrupt vector ? this field provides the number of the lowest numbered enabled transmit message buffer that has its interrupt stat us flag mbif and its interrupt enable bit mbie set. if there is no transmit message buffer with the interrupt status flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. 6-0 rbivec receive buffer interrupt vector ? this field provides the message buffer number of the lowest numbered receive message buffer which has its interrupt flag mbif and its interrupt enable bit mbie asserted. if there is no receive message buffer with the interrupt status flag mbif and the interrupt enable mbie bits asserted, the value in this field is set to 0. 0x0024 a dditional reset: run command 1514131211109876543210 r status_err_cnt w reset0000000000000000 figure 3-16. channel a status error counter register (casercr) table 3-23. casercr field descriptions field description 15?0 status_err_cnt channel status error counter ? this field provides the current va lue channel status error counter. the counter value is updated within the first ma crotick of the following slot or segment. 0x0026 additional reset: run command 1514131211109876543210 r status_err_cnt w reset0000000000000000 figure 3-17. channel b status error counter register (cbsercr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 88 freescale semiconductor this register provides the channel st atus error counter for channel b. th e protocol engine generates a slot status vector for each static slot, each dynamic slot, the symbol window, a nd the nit. the slot status vector contains the four protocol related error indicator bits vss!syntaxerror , vss!contenterror , vss!bviolation , and vss!txconflict . the flexray module increments the counter by 1 if, for a slot or se gment, at least one error bit is set to ?1?. the counter wraps around af ter it has reached the maximum value. for more information on slot status monitoring see section 3.4.18, ?slot status monitoring ?. 3.3.2.19 protocol status register 0 (psr0) this register provides information about the current protocol status. table 3-24. cbsercr field descriptions field description 15?0 status_err_cnt channel status error counter ? this field provides the current cha nnel status error count. the counter value is updated within the first macrot ick of the following slot or segment. 0x0028 1514131211109876543210 r errmode slotmode 0 protstate startupstate 0 wakeupstatus w reset0000000000000000 figure 3-18. protocol status register 0 (psr0) table 3-25. psr0 field descriptions (sheet 1 of 2) field description 15?14 errmode error mode ? protocol related variable: vpoc!errormode . this field indicates the error mode of the protocol. 00 active 01 passive 10 comm_halt 11 reserved 13?12 slotmode slot mode ? protocol related variable: vpoc!slotmode . this field indicates the slot mode of the protocol. 00 single 01 all_pending 10 all 11 reserved 10?8 protstate protocol state ? protocol related variable: vpoc!state. this field indicates t he state of the protocol. 000 poc:default config 001 poc:config 010 poc:wakeup 011 poc:ready 100 poc:normal passive 101 poc:normal active 110 poc:halt 111 poc:startup flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 89 3.3.2.20 protocol status register 1 (psr1) 7?4 startup state startup state ? protocol related variable: vpoc!startupstate. this field indicates the current sub-state of the startup procedure. 0000 reserved 0001 reserved 0010 poc:coldstart collision resolution 0011 poc:coldstart listen 0100 poc:integration consistency check 0101 poc:integrationi listen 0110 reserved 0111 poc:initialize schedule 1000 reserved 1001 reserved 1010 poc:coldstart consistency check 1011 reserved 1100 reserved 1101 poc:integration coldstart check 1110 poc:coldstart gap 1111 poc:coldstart join 2?0 wakeup status wakeup status ? protocol related variable: vpoc!wakeupstatus . this field provides the outcome of the execution of the wakeup mechanism. 000 reserved 001 received_header 010 received_wup 011 collision_header 100 collision_wup 101 collision_unknown 110 transmitted 111 reserved 0x002a additional reset: csaa, csp, cpn: r un command write: normal mode 1514131211109876543210 r csaa csp 0 remcsat cpn hhr frz aptac w reset0000000000000000 figure 3-19. protocol status register 1 (psr1) table 3-25. psr0 field descriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 90 freescale semiconductor 3.3.2.21 protocol status register 2 (psr2) this register provides a snapshot of status inform ation about the network idle time nit, the symbol window and the clock synchronizati on. the nit related status bits nbvb, nseb, nbva, and nsea are table 3-26. psr1 field descriptions field description 15 csaa cold start attempt aborted flag ? protocol related event: ?set coldstart abort indicator in chi? this flag bit is set when the flexray modulehas aborted a cold start attempt. the appl ication clears this flag by writing 1 to it. writing a 0 will not chan ge the state of the flag. if the application clears the flag while the flexray module sets the flag at the same time, then the flag is not cleared. 0 no such event 1 cold start attempt aborted 14 csp leading cold start path ? this status bit is set when the flexray module has reached the poc:normal active state via the leading cold start path. this i ndicates that this node has started the network 0 no such event 1 poc:normal active reached from poc:startup state via leading cold start path 12?8 remcsat remaining coldstart attempts ? protocol related variable: vremainingcoldstartattempts this field provides the number of remaining cold start attempts that the flexray module will execute. 7 cpn leading cold start path noise ? protocol related variable: vpoc!coldstartnoise this status bit is set if the flexray module has reached the poc:normal active state via the leading cold start path under noise conditions. this indicates there was some activity on the flexray bus while the flexray module was starting up the cluster. 0 no such event 1 poc:normal active state was reached from poc:startup state via noisy leading cold start path 6 hhr host halt request pending ? protocol related variable: vpoc!chihaltrequest this status bit is set when flexray module receives the halt command from the application via the protocol operation control register (pocr) . the flexray module clears this status bit after a hard reset condition or when the protocol is in the poc:default config state. 0 no such event 1 halt command received 5 frz freeze occurred ? protocol related variable: vpoc!freeze this status bit is set when the flexray module has reached the poc:halt state due to the host freeze command or due to an internal error condition requiring immediate halt. the flexray module clears this status bit after a hard reset condition or when the protocol is in the poc:default config state. 0 no such event 1 immediate halt due to freeze or internal error condition 4?0 aptac allow passive to active counter ? protocol related variable: vpoc!allowpassivetoactive this field provides the number of consecutive even/odd communication cycle pairs that have passed with valid rate and offset correction terms, but the protocol is still in the poc:normal passive state due to an application configured delay to enter poc:normal active state. this delay is defined by the allow_passive_to_active field in the protocol configuration register 12 (pcr12) . if this aptac counter has reach ed its maximum value, it is not incremented any more. 0x002c additional reset: run command 1514131211109876543210 r nbvb nseb stcb sbvb sseb mtb nbva nsea stca sbva ssea mta clkcorrfailcnt w reset0000000000000000 figure 3-20. protocol status register 2 (psr2) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 91 updated by the flexray module after the end of the nit a nd before the end of the first slot of the next communication cycle. the symbol wi ndow related status bits stcb , sbvb, sseb, mtb, stca, sbva, sseb, and mta are updated by the fl exray module after the end of the symbol window and before the end of the current communication cy cle. if no symbol window is configured, the symbol window related status bits remain in their rese t state. the clock sync hronization related clkcor rfailcnt is updated by the flexray module after the end of the static segment an d before the end of th e current communication cycle. table 3-27. psr2 field descriptions (sheet 1 of 2) field description 15 nbvb nit boundary violation on channel b ? protocol related variable: vss!bviolation for nit on channel b this status bit is set when there was some media activi ty on the flexray bus channel b at the end of the nit. 0 no such event 1 media activity at boundaries detected 14 nseb nit syntax error on channel b ? protocol related variable: vss!syntaxerror for nit on channel b this status bit is set when a syntax error was detected during nit on channel b. 0 no such event 1 syntax error detected 13 stcb symbol window transmit conflict on channel b ? protocol related variable: vss!txconflict for symbol window on channel b this status bit is set if there was a transmissi on conflict during the symbol window on channel b. 0 no such event 1 transmission conflict detected 12 sbvb symbol window boundary violation on channel b ? protocol related variable: vss!bviolation for symbol window on channel b this status bit is set if there was some media activity on the flexray bus channel b at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected 11 sseb symbol window syntax error on channel b ? protocol related variable: vss!syntaxerror for symbol window on channel b this status bit is set when a syntax error was detected during the symbol window on channel b. 0 no such event 1 syntax error detected 10 mtb media access test symbol mts received on channel b ? protocol related variable: vss!validmts for symbol window on channel b this status bit is set if the media access test sy mbol mts was received in the symbol window on channel b. 0 no such event 1 mts symbol received 9 nbva nit boundary violation on channel a ? protocol related variable: vss!bviolation for nit on channel a this status bit is set when there was some media activi ty on the flexray bus channel a at the end of the nit. 0 no such event 1 media activity at boundaries detected 8 nsea nit syntax error on channel a ? protocol related variable: vss!syntaxerror for nit on channel a this status bit is set when a syntax error was detected during nit on channel a. 0 no such event 1 syntax error detected flexray module (flexrayv2) mfr4300 data sheet, rev. 3 92 freescale semiconductor 3.3.2.22 protocol status register 3 (psr3) this register provides aggregated ch annel status information as an accrued status of channel activity for all communication slots, re gardless of whether they are assigne d for transmission or subscribed for reception. it provides accrued information for the sy mbol window, the nit, and the wakeup status. the application can clear a ny flag at any time by writing a '1' to it. writing a ?0? will not change the flag state. if the application tries to clear a flag while the flex ray module sets the flag at the same time, then that flag is not cleared. 7 stca symbol window transmit conflict on channel a ? protocol related variable: vss!txconflict for symbol window on channel a this status bit is set if there was a transmission conflicts during the symbol window on channel a. 0 no such event 1 transmission conflict detected 6 sbva symbol window boundary violation on channel a ? protocol related variable: vss!bviolation for symbol window on channel a this status bit is set if there was some media activity on the flexray bus channel a at the start or at the end of the symbol window. 0 no such event 1 media activity at boundaries detected 5 ssea symbol window syntax error on channel a ? protocol related variable: vss!syntaxerror for symbol window on channel a this status bit is set when a syntax error wa s detected during the symbol window on channel a. 0 no such event 1 syntax error detected 4 mta media access test symbol mts received on channel a ? protocol related variable: vss!validmts for symbol window on channel a this status bit is set if the media access test sy mbol mts was received in the symbol window on channel a. 1 mts symbol received 0 no such event 3?0 clkcorr- failcnt clock correction failed counter ? protocol related variable: vclockcorrectionfailed this field provides the number of consecutive even /odd communication cycle pairs that have passed without clock synchronization having performed an offset or a rate correction due to lack of synchronization frames. it is not incremented when it has reached the configured value of either max_without_clock_correction_fatal or max_without_clock_correction_passive as defined in the protocol configuration register 8 (pcr8) . the flexray module resets this counter on a hard reset condition, when the protocol enters the poc:normal active state, or when both the rate an d offset correction terms have been calculated successfully. 0x002e additional reset: run command write: normal mode 1514131211109876543210 r0 0 wub abvb aacb aceb aseb avfb 00 wua abva aaca acea asea avfa w reset0000000000000000 figure 3-21. protocol status register 3 (psr3) table 3-27. psr2 field descriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 93 table 3-28. psr3 field descriptions (sheet 1 of 2) field description 13 wub wakeup symbol received on channel b ? this flag is set when a wakeup symbol was received on channel b. 0 no wakeup symbol received 1 wakeup symbol received 12 abvb aggregated boundary violation on channel b ? this flag is set when a boundary violation has been detected on channel b. boundary violations are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected 11 aacb aggregated additional co mmunication on channel b ? this flag is set when at least one valid frame was received on channel b in a slot that also contained an additional communication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected 10 aceb aggregated content error on channel b ? this flag is set when a content error has been detected on channel b. content errors are detected in the communication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected 9 aseb aggregated syntax error on channel b ? this flag is set when a synta x error has been detected on channel b. syntax errors are detected in the co mmunication slots, the symbol window and the nit. 0 no syntax error detected 1 syntax errors detected 8 avfb aggregated valid frame on channel b ? this flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel b. 1 at least one syntactically valid frame received 0 no syntactically valid frames received 5 wua wakeup symbol received on channel a ? this flag is set when a wakeup symbol was received on channel a. 0 no wakeup symbol received 1 wakeup symbol received 4 abva aggregated boundary violation on channel a ? this flag is set when a boundary violation has been detected on channel a. boundary violat ions are detected in the communication slots, the symbol window, and the nit. 0 no boundary violation detected 1 boundary violation detected 3 aaca aggregated additional co mmunication on channel a ? this flag is set when a valid frame was received in a slot on channel a that also contained an additional co mmunication with either syntax error, content error, or boundary violations. 0 no additional communication detected 1 additional communication detected 2 acea aggregated content error on channel a ? this flag is set when a content error has been detected on channel a. content errors are detected in the co mmunication slots, the symbol window, and the nit. 0 no content error detected 1 content error detected flexray module (flexrayv2) mfr4300 data sheet, rev. 3 94 freescale semiconductor 3.3.2.23 macrotick counter register (mtctr) this register provides the macrotick c ount of the current communication cycle. 3.3.2.24 cycle counter register (cyctr) this register provides the number of the current communication cycle. 1 asea aggregated syntax error on channel a ? this flag is set when a syntax error has been detected on channel a. syntax errors are detected in the comm unication slots, the symbol window, and the nit. 0 no syntax error detected 1 syntax errors detected 0 avfa aggregated valid frame on channel a ? this flag is set when a syntactically correct valid frame has been received in any static or dynamic slot through channel a. 0 no syntactically valid frames received 1 at least one syntactically valid frame received 0x0030 1514131211109876543210 r0 0 mtct w reset0000000000000000 figure 3-22. macrotick counter register (mtctr) table 3-29. mtctr field descriptions field description 13?0 mtct macrotick counter ? protocol related variable: vmacrotick this field provides the macrotick count of the current communication cycle. 0x0032 1514131211109876543210 r0000000000 cy ccnt w reset0000000000000000 figure 3-23. cycle counter register (cyctr) table 3-30. cyctr field descriptions field description 5?0 cyccnt cycle counter ? protocol related variable: vcyclecounter this field provides the numb er of the current communication cycle. if the counter reaches the maximum value of 63, the counter wraps and starts from zero again. table 3-28. psr3 field descriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 95 3.3.2.25 slot counter channel a register (sltctar) this register provides the number of the current slot in the curren t communication cycle for channel a. 3.3.2.26 slot counter chan nel b register (sltctbr) this register provides the number of the current slot in the curren t communication cycle for channel b. 3.3.2.27 rate correction value register (rtcorvr) this register provides the sign extende d rate correction value in microticks as it was calculated by the clock synchronization algorithm. the flexray module update s this register during the nit of each odd numbered communication cycle. 0x0034 1514131211109876543210 r00000 slotcnta w reset0000000000000000 figure 3-24. slot counter channel a register (sltctar) table 3-31. sltctar field descriptions field description 10?0 slotcnta slot counter value for channel a ? protocol related variable: vslotcounter for channel a this field provides the number of the curr ent slot in the current communication cycle. 0x0036 1514131211109876543210 r00000 slotcntb w reset0000000000000000 figure 3-25. slot counter channel b register (sltctbr) table 3-32. sltctbr field descriptions field description 10?0 slotcnta slot counter value for channel b ? protocol related variable: vslotcounter for channel b this field provides the number of the curr ent slot in the current communication cycle. 0x0038 additional reset: run command 1514131211109876543210 rratecorr w reset0000000000000000 figure 3-26. rate correction value register (rtcorvr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 96 freescale semiconductor 3.3.2.28 offset correction value register (ofcorvr) this register provides the sign extend ed offset correction value in micro ticks as it was calculated by the clock synchronization algorithm. the flexray module updates this register during the nit. 3.3.2.29 combined interrupt flag register (cifrr) table 3-33. rtcorvr field descriptions field description 15?0 ratecorr rate correction value ? protocol related variable: vratecorrection (before value limitation and external rate correction) this field provides the sign extended rate correction value in microticks as it was calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the applicat ion of the external rate correction. if the magnitude of the internally calculated rate correction value exceeds the limit given by rate_correction_out in the protocol configuration register 13 (pcr13) , the clock correction reached limit interrupt flag ccl_if is set in the protocol interrupt flag register 0 (pifr0) . note: if the flexray module was not able to calculate a new rate correction term due to a lack of synchronization frames, the ratecorr value is not updated. 0x003a additional reset: run command 1514131211109876543210 r offsetcorr w reset0000000000000000 figure 3-27. offset correction value register (ofcorvr) table 3-34. ofcorvr field descriptions field description 15?0 offset- corr offset correction value ? protocol related variable: voffsetcorrection (before value limitation and external offset correction) this field provides the sign extended offset correction value in microticks as it wa s calculated by the clock synchronization algorithm. the value is represented in 2?s complement format. this value does not include the value limitation and the application of the external offset correction. if the magnitude of the internally calculated rate correction value exceeds the limit giv en by offset_correction_out field in the protocol configuration register 29 (pcr29) , the clock correction reached limit interrupt flag ccl_if is set in the protocol interrupt flag register 0 (pifr0) . note: if the flexray module was not able to calculate an new offset correction term due to a lack of synchronization frames, the offsetcorr value is not updated. 0x003c 1514131211109876543210 r 00000000mifprifchif wupif fnebif fneaif rbif tbif w reset0000000000000000 figure 3-28. combined interrupt flag register (cifrr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 97 this register provides five combined interrupt flag s and a copy of three individual interrupt flags. the combined interrupt flags are the result of a binary or of the values of other interrupt flags regardless of the state of the interrupt enable bits . the generation scheme for the combin ed interrupt flags is depicted in figure 3-143 . the individual interrupt flags wupif, fneb if, and fneaif are copies of corresponding flags in the global interrupt flag and enable register (gifer) and are provided here to simplify the application interrupt flag check. to clear the indivi dual interrupt flags, the application must use the global interrupt flag and enable register (gifer) . note the meanings of the five combined st atus bits mif, prif, chif, rbif, and tbif are different from those mentioned in the global interrupt flag and enable register (gifer) . table 3-35. cifrr field descriptions field description 7 mif module interrupt flag ? this flag is set if there is at least one interrupt source that has its interrupt flag asserted. 0 no interrupt source has its interrupt flag asserted 1 at least one interrupt source has its interrupt flag asserted 6 prif protocol interrupt flag ? this flag is set if at least one of the individual protocol interrupt flags in the protocol interrupt flag register 0 (pifr0) or protocol interrupt flag register 1 (pifr1) is equal to 1. 0 all individual protocol interrupt flags are equal to 0 1 at least one of the individual protocol interrupt flags is equal to 1 5 chif chi interrupt flag ? this flag is set if at least one of the individual chi error flags in the chi error flag register (chierfr) is equal to 1. 0 all chi error flags are equal to 0 1 at least one chi error flag is equal to 1 4 wupif wakeup interrupt flag ? copy of gifer.wupif 3 fnebif receive fifo channel b not empty interrupt flag ? copy of gifer.fnebif 2 fneaif receive fifo channel a not empty interrupt flag ? copy of gifer.fneaif 1 rbif receive message buffer interrupt flag ? this flag is set if for at least one of the individual receive message buffers (mbccsn.mtd = 0) the interrupt flag mbif in the corresponding message buffer configuration, control, status registers (mbccsrn) is equal to 1. 0 none of the individual receive message buffers has the mbif flag asserted. 1 at least one individual receive message buffers has the mbif flag asserted. 0 tbif transmit message buffer interrupt flag ? this flag is set if for at least one of the individual single or double transmit message buffers (mbccsn.mtd = 1) the interrupt flag mbif in the corresponding message buffer configuration, control, status registers (mbccsrn) is equal to 1. 0 none of the individual transmit message buffers has the mbif flag asserted. 1 at least one individual transmit message buffers has the mbif flag asserted. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 98 freescale semiconductor 3.3.2.30 sync frame counter register (sfcntr) this register provides the number of synchronization fram es that are used for cl ock synchronization in the last even and in the last odd numbered communication cy cle. this register is upd ated after the nit start and before 10 mt after offset correction start. note if the application has locked the even synchronization table at the end of the static segment of an even communica tion cycle, the flexray module will not update the fields sfevb and sfeva. if the application has locked the odd sy nchronization table at the end of the static segment of an odd communication cycle, the flexray module will not update the values sfodb and sfoda. 3.3.2.31 sync frame table offset register (sftor) this register defines the frm related offset for sync frame tables. for more details, see section 3.4.12, ?sync frame id and sync frame deviation tables ?. 0x0040 additional reset: run command 1514131211109876543210 r sfevb sfeva sfodb sfoda w reset0000000000000000 figure 3-29. sync frame counter register (sfcntr) table 3-36. sfcntr field descriptions field description 15?12 sfevb sync frames channel b, even cycle ? protocol related variable: size of ( vssyncidlistb for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. 11?8 sfevb sync frames channel a, even cycle ? protocol related variable: size of ( vssyncidlista for even cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. 7?4 sfodb sync frames channel b, odd cycle ? protocol related variable: size of ( vssyncidlistb for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. 3?0 sfoda sync frames channel a, odd cycle ? protocol related variable: size of ( vssyncidlista for odd cycle) this field provides the size of the internal list of frame ids of received synchronization frames used for clock synchronization. 0x0042 write: poc:config 1514131211109876543210 r sft_offset[15:1] 0 w reset0000000000000000 figure 3-30. sync frame table offset register (sftor) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 99 3.3.2.32 sync frame table configuration, control, status register (sftccsr) this register provides configurati on, control, and status information related to the generation and access of the clock sync id tables and clock sync m easurement tables. for a detailed description, see section 3.4.12, ?sync frame id and sync frame deviation tables ?. table 3-37. sftor field description field description 15?1 sftor sync frame table offset ? offset of the sync frame tables in the frm. this offset is required to be 16-bit aligned. thus stf_offset[0] is always 0. 0x0044 write: normal mode 1514131211109876543210 r 0 0 cycnum elks olks eval oval 0 0 sdven siden w elkt olkt opt reset0000000000000000 figure 3-31. sync frame table configuration, control, status register (sftccsr) table 3-38. sftccsr field descriptions (sheet 1 of 2) field description 15 elkt even cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the even cycle tables. 0no effect 1 triggers lock/unlock of the even cycle tables. 14 olkt odd cycle tables lock/unlock trigger ? this trigger bit is used to lock and unlock the odd cycle tables. 0no effect 1 triggers lock/unlock of the odd cycle tables. 13?8 cycnum cycle number ? this field provides the number of the cycle in which the curr ently locked table was recorded. if none or both tables are locked, this value is related to the even cycle table. 7 elks even cycle tables lock status ? this status bit indicates whether the application has locked the even cycle tables. 0 application has not locked the even cycle tables. 1 application has locked the even cycle tables. 6 olks odd cycle tables lock status ? this status bit indica tes whether the applicatio n has locked the odd cycle tables. 0 application has not locked the odd cycle tables. 1 application has locked the odd cycle tables. 5 eval even cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the even cycle are valid. the flexray module cl ears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent). 4 oval odd cycle tables valid ? this status bit indicates whether the sync frame id and sync frame deviation tables for the odd cycle are valid. the fl exray module clears this status bit when it starts updating the tables, and sets this bit when it has finished the table update. 0 tables are not valid (update is ongoing) 1 tables are valid (consistent). flexray module (flexrayv2) mfr4300 data sheet, rev. 3 100 freescale semiconductor 3.3.2.33 sync frame id rejectio n filter register (sfidrfr) this register defines the s ync frame rejection filter id. the application must upda te this register outside of the static segment. if the applic ation updates this register in the stat ic segment, it can appear that the flexray module accepts the sync frame in the current cycle. 2 opt one pair trigger ? this trigger bit controls whether the flexra y module writes continuously or only one pair of sync frame tables into the frm. if this trigger is set to ?1? while sdven or siden is se t to ?1?, the flexray module writes only one pair of the enabled sync frame tables corresponding to the next even-odd-cycle pair into the frm. in this case, the flexray module clears the sdven or siden bits immediately. if this trigger is set to ?0? while sdven or siden is set to ?1?, the flexray module writes continuously the enabled sync frame tables into the frm. 0 write continuously pairs of enabled sync frame tables into frm. 1 write only one pair of enabled sync frame tables into frm. 1 sdven sync frame deviation table enable ? this bit controls the generation of the sync frame deviation tables. the application must set this bit to re quest the flexray module to write the sync frame deviation tables into the frm. 0 do not write sync frame deviation tables 1 write sync frame deviation tables into frm note: if the application sets sdven to ?1?, then the application must set siden to ?1? too. 0 siden sync frame id table enable ? this bit controls the generation of the sync frame id tables. the application must set this bit to ?1? to request the flex ray module to write the sync frame id tables into the frm. 0 do not write sync frame id tables 1 write sync frame id tables into frm 0x0046 16-bit write access required write: normal mode 1514131211109876543210 r000000 synfrid w reset0000000000000000 figure 3-32. sync frame id reje ction filter register (sfidrfr) table 3-39. sfidrfr field descriptions field description 9?0 synfrid sync frame rejection id ? this field defines the frame id of a frame that must not be used for clock synchronization. for details see section 3.4.15.2, ?sync frame rejection filtering? . table 3-38. sftccsr field descriptions (sheet 2 of 2) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 101 3.3.2.34 sync frame id acceptance filter value register (sfidafvr) this register defines the sync frame acceptanc e filter value. for details on filtering, see section 3.4.15, ?sync frame filtering ?. 3.3.2.35 sync frame id acceptance filter mask register (sfidafmr) this register defines the sync frame accepta nce filter mask. for details on filtering see section 3.4.15.1, ?sync frame acceptance filtering? . 3.3.2.36 network management vector registers (nmvr0?nmvr5) each of these six registers holds one part of the network management vector. the length of the network management vector is configured in the network management vector length register (nmvlr) . if nmvlr is programmed with a valu e that is less than 12 bytes, the remaining bytes of the network 0x0048 write: poc:config 1514131211109876543210 r000000 fval w reset0000000000000000 figure 3-33. sync frame id acceptance filter value register (sfidafvr) table 3-40. sfidafvr field descriptions field description 9?0 fval filter value ? this field defines the value for the sync frame acceptance filtering. 0x004a write: poc:config 1514131211109876543210 r000000 fmsk w reset0000000000000000 figure 3-34. sync frame id acceptance filter mask register (sfidafmr) table 3-41. sfidafmr field descriptions field description 9?0 fmsk filter mask ? this field defines the mask for the sync frame acceptance filtering. 0x004c, 0x004e, 0x0050, 0x0052, 0x0054, 0x0056 1514131211109876543210 r nmvp[15:8] nmvp[7:0] w reset0000000000000000 figure 3-35. network management vector registers (nmvr0?nmvr5) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 102 freescale semiconductor management vector registers (nmvr0?nmvr5) , which are not used for the network management vector accumulating, will remain 0?s. the nmvr provides accrued information over all recei ved nmvs in the last communication cycle. all nmvs received in one cycle are ored into the nmvr. the nmvr is updated at the end of the communication cycle. 3.3.2.37 network management ve ctor length register (nmvlr) this register defines the length of th e network management vector in bytes. table 3-42. nmvr[0:5] field descriptions field description 15?0 nmvp network management vector part ? the mapping between the network management vector registers (nmvr0?nmvr5) and the receive message buffer payload bytes in nmv[0:11] is depicted in table 3-43 . table 3-43. mapping of nmvrn to the received payload bytes nmvn nmvrn register nmvn received payload nmvr0.nmvp[15:8] nmv0 nmvr0.nmvp[7:0] nmv1 nmvr1.nmvp[15:8] nmv2 nmvr1.nmvp[7:0] nmv3 ... nmvr5.nmvp[15:8] nmv10 nmvr5.nmvp[7:0] nmv11 0x0058 write: poc:config 1514131211109876543210 r000000000000 nmvl w reset0000000000000000 figure 3-36. network management vector length register (nmvlr) table 3-44. nmvlr field descriptions field description 3?0 nmvl network management vector length ? protocol related variable: gnetworkmanagementvectorlength this field defines the length of th e network management vector in byte s. legal values are between 0 and 12. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 103 3.3.2.38 timer configuration a nd control register (ticcr) this register is used to configure and contro l the timers t1 and t2. for timer details, see section 3.4.17, ?timer support? . timer t1 is an absolute timer. timer t2 can be configured as an absolute or relative timer. note both timers are deactivated immediatel y when the protocol enters a state different from poc:normal active or poc:normal passive . 0x005a write: t2_cfg: poc:config write: t2_rep, t1_rep, t1sp, t2sp, t1tr, t2tr: normal mode 1514131211109876543210 r0 0 t2_cfg t2_rep 000t2st000 t1_ rep 000t1st w t2sp t2tr t1sp t1tr reset0000000000000000 figure 3-37. timer configuratio n and control register (ticcr) table 3-45. ticcr field descriptions field description 13 t2_cfg timer t2 configuration ? this bit configures the timebase mode of timer t2. 0 t2 is absolute timer. 1 t2 is relative timer. 12 t2_rep timer t2 repetitive mode ? this bit configures the repetition mode of timer t2. 0 t2 is non repetitive 1 t2 is repetitive 10 t2sp timer t2 stop ? this trigger bit is used to stop timer t2. 0 no effect 1 stop timer t2 9 t2tr timer t2 trigger ? this trigger bit is used to start timer t2. 0 no effect 1 start timer t2 8 t2st timer t2 state ? this status bit provides t he current state of timer t2. 0 timer t2 is idle 1 timer t2 is running 4 t1_rep timer t1 repetitive mode ? this bit configures the repetition mode of timer t1. 0 t1 is non repetitive 1 t1 is repetitive 2 t1sp timer t1 stop ? this trigger bit is used to stop timer t1. 0 no effect 1 stop timer t1 1 t1tr timer t1 trigger ? this trigger bit is used to start timer t1. 0 no effect 1 start timer t1 0 t1st timer t1 state ? this status bit provides t he current state of timer t1. 0 timer t1 is idle 1 timer t1 is running flexray module (flexrayv2) mfr4300 data sheet, rev. 3 104 freescale semiconductor 3.3.2.39 timer 1 cycle set register (ti1cysr) this register defines the cycle filter value and the cycle filter mask for timer t1. for a detailed description of timer t1, refer to section 3.4.17.1, ?absolute timer t1? . note if this register is modified whil e timer is running, the change becomes effective immediately. 3.3.2.40 timer 1 macrotick o ffset register (ti1mtor) this register holds the macrotick offs et value for timer t1. for a detailed description of timer t1, refer to section 3.4.17.1, ?absolute timer t1? . note if the application modifies the value in this register while the timer is running, the change becomes effective immediately and timer t1 will expire according to the changed value. 0x005c write: any time 1514131211109876543210 r0 0 t1_cyc_val 00 t1_cyc_msk w reset0000000000000000 figure 3-38. timer 1 cycle set register (ti1cysr) table 3-46. ti1cysr field descriptions field description 13?8 t1_cyc_val timer t1 cycle filter value ? this field defines the cycle filter value for timer t1. 5?0 t1_cyc_msk timer t1 cycle filter mask ? this field defines the cycle filter mask for timer t1. 0x005e write: any time 1514131211109876543210 r0 0 t1_mtoffset w reset0000000000000000 figure 3-39. timer 1 macrotick offset register (ti1mtor) table 3-47. ti1mtor field descriptions field description 13?0 t1_mtoffset timer 1 macrotick offset ? this field defines the macrotick offset value for timer 1. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 105 3.3.2.41 timer 2 configuration register 0 (ti2cr0) the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (ticcr) . for a detailed description of timer t2, refer to section 3.4.17.2, ?absolute / relative timer t2? . note if timer t2 is configured as an absolute timer and the appl ication modifies the values in this register while th e timer is running, the change becomes effective immediately and timer t2 will expire according to the changed values. if timer t2 is configured as a relative timer and the app lication changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. 0x0060 write: any time 1514131211109876543210 r0 0 t2_cyc_val 00 t2_cyc_msk w r t2_mtcnt[31:16] w reset0000000000000000 figure 3-40. timer 2 configuration register 0 (ti2cr0) table 3-48. ti2cr0 field descriptions field description fields for absolute timer t2 (ticcr.t2_cfg = ?0?) 13?8 t2_cyc_val timer t2 cycle filter value ? this field defines the cycl e filter value for timer t2. 5?0 t2_cyc_msk timer t2 cycle filter mask ? this field defines the cycle filter mask for timer t2. fields for relative timer t2 (ticcr.t2_cfg = ?1?) 15?0 t2_mtcnt[31:16] timer t2 macrotick high word ? this field defines the high word of the macrotick count for timer t2. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 106 freescale semiconductor 3.3.2.42 timer 2 configuration register 1 (ti2cr1) the content of this register depends on the value of the t2_cfg bit in the timer configuration and control register (ticcr) . for a detailed description of timer t2, refer to section 3.4.17.2, ?absolute / relative timer t2? . note if timer t2 is configured as an absolute timer and the appl ication modifies the values in this register while th e timer is running, the change becomes effective immediately and th e timer t2 will expire according to the changed values. if timer t2 is configured as a relative timer and the app lication changes the values in this register while the timer is running, the change becomes effective when the timer has expired according to the old values. 3.3.2.43 slot status selection register (sssr) this register is used to access th e four internal non memo ry-mapped slot status selection registers sssr0 to sssr3. each internal registers sel ects a slot, or symbol window/nit, whose status vector will be saved 0x0062 write: any time 1514131211109876543210 r0 0 t2_mtoffset w r t2_mtcnt[15:0] w reset0000000000000000 figure 3-41. timer 2 configuration register 1 (ti2cr1) table 3-49. ti2cr1 field descriptions field description fields for absolute timer t2 (ticcr.t2_cfg = ?0?) 13?0 t2_mtoffset timer t2 macrotick offset ? this field holds the macrotick offset value for timer t2. fields for relative timer t2 (ticcr.t2_cfg = ?1?) 15?0 t2_mtcnt[15:0] timer t2 macrotick low word ? this field defines the low word of the macrotick value for timer t2. 0x0064 16-bit write access required write: any time 1514131211109876543210 r0 0 sel 0 slotnumber wwmd reset0000000000000000 figure 3-42. slot status selection register (sssr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 107 in the corresponding slot status registers (ssr0?ssr7) according to table 3-51 . for a detailed description of slot status monitoring, refer to section 3.4.18, ?slot status monitoring ?. 3.3.2.44 slot status counter condition register (ssccr) this register is used to access and program the f our internal non-memory mapped slot status counter condition registers ssccr0 to ssccr3. each of these four internal slot status counter condition registers defines the mode and the conditions for incrementing the counter in the corresponding slot status counter registers (sscr0?sscr3) . the correspondence is given in table 3-53 . for a detailed description of slot status counters, refer to section 3.4.18.4, ?slot status counter registers ?. table 3-50. sssr fi eld descriptions field description 15 wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. 13?12 sel selector ? this field selects one of the four internal slot status selection registers for access. 00 select sssr0. 01 select sssr1. 10 select sssr2. 11 select sssr3. 10?0 slotnumber slot number ? this field specifies the number of the slot whose status will be saved in the corresponding slot status registers. note: if this value is set to 0, the related slot status re gister provides the status of the symbol window after the nit start, and provides the status of the nit after the cycle start. table 3-51. mapping between sssrn and ssrn internal slot status selection register write the slot status of the slot selected by sssrn for each even communication cycle odd communication cycle for channel b to for channel a to for channel b to for channel a to sssr0 ssr0[15:8] ssr0[7: 0] ssr1[15:8 ] ssr1[7:0] sssr1 ssr2[15:8] ssr2[7: 0] ssr3[15:8 ] ssr3[7:0] sssr2 ssr4[15:8] ssr4[7: 0] ssr5[15:8 ] ssr5[7:0] sssr3 ssr6[15:8] ssr6[7: 0] ssr7[15:8 ] ssr7[7:0] 0x0066 16-bit write access required write: any time 1514131211109876543210 r0 0 sel 0 cntcfg mcy vfr syf nuf suf statusmask wwmd reset0000000000000000 figure 3-43. slot status counter condition register (ssccr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 108 freescale semiconductor table 3-52. ssccr field descriptions field description 15 wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel field only on write access. 13?12 sel selector ? this field selects one of the four internal slot counter conditio n registers for access. 00 select ssccr0. 01 select ssccr1. 10 select ssccr2. 11 select ssccr3. 10?9 cntcfg counter configuration ? these bit field controls the channel relat ed incrementing of the slot status counter. 00 increment by 1 if condition is fulfilled on channel a. 01 increment by 1 if condition is fulfilled on channel b. 10 increment by 1 if condition is fulfilled on at least one channel. 11 increment by 2 if condition is fulfilled on both channels channel. increment by 1 if condition is fulfilled on only one channel. 8 mcy multi cycle selection ? this bit defines whether the slot status counter accumulates over multiple communication cycles or provides information for the previ ous communication cycle only. 0 the slot status counter prov ides information for the previous communication cycle only. 1 the slot status counter accumulate s over multiple communication cycles. 7 vfr valid frame restriction ? this bit is used to restrict the counter to received valid frames. 0 the counter is not restricted to valid frames only. 1 the counter is restricted to valid frames only. 6 syf sync frame restriction ? this bit is used to restrict the counter to received frames with the sync frame indicator bit set to ?1?. 0 the counter is not restricted with re spect to the sync frame indicator bit. 1 the counter is restricted to frames with the sync frame indicator bit set to ?1?. 5 nuf null frame restriction ? this bit is used to restrict the coun ter to received frames with the null frame indicator bit set to ?0?. 0 the counter is not restricted with respect to the null frame indicator bit. 1 the counter is restricted to frames with the null frame indicator bit set to ?0?. 4 suf startup frame restriction ? this bit is used to restrict the counter to received frames with the startup frame indicator bit set to ?1?. 0 the counter is not restricted with respect to the startup frame indicator bit. 1 the counter is restricted to received frames with the startup frame indicator bit set to ?1?. 3?0 statusmask slot status mask ? this bit field is used to enable the counte r with respect to the four slot status error indicator bits. statusmask[3] ? this bit enables the counting for slots with the syntax error indicator bit set to ?1?. statusmask[2] ? this bit enables the counting for slots with the content error indicator bit set to ?1?. statusmask[1] ? this bit enables the counting for slots with the boundary violation indicator bit set to ?1?. statusmask[0] ? this bit enables the counting for slots with the transmission conflict indicator bit set to ?1?. table 3-53. mapping between internal ssccrn and sscrn condition register condition defined for register ssccr0 sscr0 ssccr1 sscr1 ssccr2 sscr2 ssccr3 sscr3 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 109 3.3.2.45 slot status registers (ssr0?ssr7) each of these eight register s holds the status vector of the slot sp ecified in the corresponding internal slot status selection register, whic h can be programmed using the slot status selection register (sssr) . each register is updated after the end of the corresponding slot as shown in figure 3-139 . the register bits are directly related to the pr otocol variables and described in more detail in section 3.4.18, ?slot status monitoring ?. 0x0068, 0x006a, 0x006c, 0x006e, 0x0070, 0x0072, 0x0074, 0x0076 1514131211109876543210 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca w reset0000000000000000 figure 3-44. slot status registers (ssr0?ssr7) table 3-54. ssr0?ssr7 field descriptions field description 15 vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = ?0? 1 vss!validframe = ?1? 14 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = ?0? 1 vrf!header!syfindicator = ?1? 13 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = ?0? 1 vrf!header!nfindicator = ?1? 12 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = ?0? 1 vrf!header!sufindicator = ?1? 11 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = ?0? 1 vss!syntaxerror = ?1? 10 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = ?0? 1 vss!contenterror = ?1? 9 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = ?0? 1 vss!bviolation = ?1? 8 tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = ?0? 1 vss!txconflict = ?1? 7 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = ?0? 1 vss!validframe = ?1? 6 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = ?0? 1 vrf!header!syfindicator = ?1? flexray module (flexrayv2) mfr4300 data sheet, rev. 3 110 freescale semiconductor 3.3.2.46 slot status counter registers (sscr0?sscr3) additional reset: [run command] each of these four registers provide s the slot status counter value for the previous communication cycle(s) and is updated at each cycle start. the value depends on the control bi ts and fields in the related internal slot status counter condition register , which can be programmed by using the slot status counter condition register (ssccr) . for more details, see section 3.4.18.4, ?slot status counter registers ?. note if the counter has reached its ma ximum value 0xffff and is in the multicycle mode, i.e. ssccrx.mcy = ?1?, the counter is not reset to 0x0000. the application can reset the c ounter by clearing the mcy bit and waiting for the next cycle start, when the flexray module clears the counter. subsequently, the counter can be se t into the multicycle mode again. 5 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = ?0? 1 vrf!header!nfindicator = ?1? 4 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = ?0? 1 vrf!header!sufindicator = ?1? 3 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = ?0? 1 vss!syntaxerror = ?1? 2 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = ?0? 1 vss!contenterror = ?1? 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = ?0? 1 vss!bviolation = ?1? 0 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = ?0? 1 vss!txconflict = ?1? 0x0078, 0x007a, 0x007c, 0x007e 1514131211109876543210 r slotstatuscnt w reset0000000000000000 figure 3-45. slow status coun ter registers (sscr0?sscr3) table 3-54. ssr0?ssr7 field descriptions (continued) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 111 3.3.2.47 mts a configurat ion register (mtsacfr) this register controls the transmission of the me dia access test symbol mt s on channel a. for more details, see section 3.4.13, ?mts generation ?. 3.3.2.48 mts b configurat ion register (mtsbcfr) this register controls the transmission of the me dia access test symbol mts on channel b. for more details, see section 3.4.13, ?mts generation? . table 3-55. sscr0?sscr3 field descriptions field description 15?0 slotstatuscnt slot status counter ? this field provides the current value of the slot status counter. 0x0080 write: cyccntmsk, cyccntval: poc:config write: mte: any time 1514131211109876543210 r mte 0 cyccntmsk 00 cyccntval w reset0000000000000000 figure 3-46. mts a configur ation register (mtsacfr) table 3-56. mtsacfr field descriptions field description 15 mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled 13?8 cyccntmsk cycle counter mask ? this field provides the filter mask for the mts cycle count filter. 5?0 cyccntval cycle counter value ? this field provides the filter value for the mts cycle count filter. 0x0082 write: cyccntmsk, cyccntval: poc:config write: mte: any time 1514131211109876543210 r mte 0 cyccntmsk 00 cyccntval w reset0000000000000000 figure 3-47. mts b configuration register (mtsbcfr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 112 freescale semiconductor 3.3.2.49 receive shadow buffer index register (rsbir) this register is used to provide and retrieve the indices of the message buffer header fields currently associated with the receive shadow buffers. for more details on the receive shadow buffer concept, refer to section 3.4.6.3.6, ?receive shadow buffers concept ?. table 3-57. mtsbcfr field descriptions field description 15 mte media access test symbol transmission enable ? this control bit is used to enable and disable the transmission of the media access test symbol in the selected set of cycles. 0 mts transmission disabled 1 mts transmission enabled 13?8 cyccntmsk cycle counter mask ? this field provides the filter mask for the mts cycle count filter. 5?0 cyccntval cycle counter value ? this field provides the filter value for the mts cycle count filter. 0x0084 16-bit write access required write: wmd, sel: any time write: rsbidx: poc:config 1514131211109876543210 r0 0 sel 0000 rsbidx wwmd reset0000000000000000 figure 3-48. receive shadow buffer index register (rsbir) table 3-58. rsbir field descriptions field description 15 wmd write mode ? this bit controls the write mode for this register. 0 update sel and rsbidx field on register write 1 update only sel field on register write 13?12 sel selector ? this field is used to select the internal receive shadow buffer index register for access. 00 rsbir_a1 ? receive shadow buffer index register for channel a, segment 1 01 rsbir_a2 ? receive shadow buffer index register for channel a, segment 2 10 rsbir_b1 ? receive shadow buffer index register for channel b, segment 1 11 rsbir_b2 ? receive shadow buffer index register for channel b, segment 2 7?0 rsbidx receive shadow buffer index ? this field contains the current index of the message buffer header field of the receive shadow message buffer selected by the sel field. the flexray module uses this index to determine the physical location of the shadow buffer header field in the flexray memory. the flexray module will update this field during receive operation.the application provides initial message buffer header index value in the configuration phase. flexray module: updates the message buffer header index after successful reception. application: provides initial message buffer header index. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 113 3.3.2.50 receive fifo selection register (rfsr) this register is used to select a receiver fifo for subsequent access th rough the receiver fifo configuration registers summarized in table 3-59 . 3.3.2.51 receive fifo start index register (rfsir) this register defines the message buffer header index of the firs t message buffer that belongs to the selected receive fifo. 0x0086 write: any time 1514131211109876543210 r000000000000000 sel w reset0000000000000000 figure 3-49. receive fifo selection register (rfsr) table 3-59. sel controlled receiver fifo registers register receive fifo start index register (rfsir) receive fifo depth and size register (rfdsr) receive fifo message id acceptance filter value register (rfmidafvr) receive fifo message id acceptance filter mask register (rfmiafmr) receive fifo frame id rejection f ilter value register (rffidrfvr) receive fifo frame id rejection filter mask register (rffidrfmr) receive fifo range filter configuration register (rfrfcfr) receive fifo range filter control register (rfrfctr) table 3-60. rfsr field descriptions field description 0 sel select ? this control bit selects the receiver fifo for subsequent programming. 0 receiver fifo for channel a selected 1 receiver fifo for channel b selected 0x0088 write: poc:config 1514131211109876543210 r00000000 sidx w reset0000000000000000 figure 3-50. receive fifo start index register (rfsir) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 114 freescale semiconductor 3.3.2.52 receive fifo depth and size register (rfdsr) this register defines the structure of the selected receive fifo, i.e. the number of entries and the size of each entry. 3.3.2.53 receive fifo a read index register (rfarir) this register provides the message buffer header index of the next available entr y of receive fifo a that the application can read. table 3-61. rfsir field descriptions field description 7?0 sidx start index ? this field defines the number of the message buff er header field of the first message buffer of the selected receive fifo. the flexray module uses the value of the sidx field to determine the physical location of the receiver fifo?s first message buffer header field. 0x008a write: poc:config 1514131211109876543210 r fifo_depth 0 entry_size w reset0000000000000000 figure 3-51. receive fifo depth and size register (rfdsr) table 3-62. rfdsr field descriptions field description 15?8 fifo_depth fifo depth ? this field defines the depth of the selected receive fifo, i.e. the number of entries. 6?0 entry_size entry size ? this field defines the size of the frame data sections for the selected receive fifo in 2 byte entities. 0x008c 1514131211109876543210 r00000000 rdidx w reset0000000000000000 figure 3-52. receive fifo a re ad index register (rfarir) table 3-63. rfarir field descriptions field description 7?0 rdidx read index ? this field provides the message buffer header in dex of the next available receive fifo message buffer that the application can read. the flexray module increments this index when the application writes to the fneaif flag in the global interrupt flag and enable register (gifer) . the index wraps back to the first message buffer header index if the end of the fifo was reached. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 115 note if the receive fifo not empty flag fn eaif is not set, the rdidx fields points to an physical messag e buffers that is invali d. only when fneaif is set, the message buffer indicated by rdidx contains valid data. 3.3.2.54 receive fifo b read index register (rfbrir) this register provides the message buffer header index of the next available entr y of receive fifo a that the application can read. note if the receive fifo not empty flag fn ebif is not set, the rdidx fields points to an physical message buffers that is invalid. only when fnebif is set, the message buffer indicated by rdidx contains valid data. 3.3.2.55 receive fifo message id a cceptance filter value register (rfmidafvr) this register defines the filter value for the message id acceptance filter of the selected receive fifo. for details on message id filtering see section 3.4.9.5, ?receive fifo filtering? . 0x008e 1514131211109876543210 r00000000 rdidx w reset0000000000000000 figure 3-53. receive fifo b read index register (rfbrir) table 3-64. rfbrir field descriptions field description 7?0 rdidx read index ? this field provides the message buffer header in dex of the next available receive fifo entry that the application can read. the flexray module increments this index when the application writes to the fnebif flag in the global interrupt flag and enable register (gifer) .the index wraps back to the first message buffer header index if the end of the fifo was reached. 0x0090 write: poc:config 1514131211109876543210 r midafval w reset0000000000000000 figure 3-54. receive fifo message id acceptance filter value register (rfmidafvr) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 116 freescale semiconductor 3.3.2.56 receive fifo message id accepta nce filter mask register (rfmiafmr) this register defines the f ilter mask for the message id acceptance fi lter of the selected receive fifo. for details on message id filtering see section 3.4.9.5, ?receive fifo filtering? . 3.3.2.57 receive fifo frame id rejectio n filter value register (rffidrfvr) this register defines the filter va lue for the frame id rejection filter of the selected receive fifo. for details on frame id filtering see section 3.4.9.5, ?receive fifo filtering? . table 3-65. rfmidafvr field descriptions field description 15?0 midafval message id acceptance filter value ? filter value for the message id acceptance filter. 0x0092 write: poc:config 1514131211109876543210 r midafmsk w reset0000000000000000 figure 3-55. receive fifo message id acceptance filter mask register (rfmiafmr) table 3-66. rfmiafmr field descriptions field description 15?0 midafmsk message id acceptance filter mask ? filter mask for the messa ge id acceptance filter. 0x0094 write: poc:config 1514131211109876543210 r00000 fidrfval w reset0000000000000000 figure 3-56. receive fifo frame id reje ction filter value register (rffidrfvr) table 3-67. rffidrfvr field descriptions field description 10?0 fidrfval frame id rejection filter value ? filter value for the frame id rejection filter. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 117 3.3.2.58 receive fifo frame id rejectio n filter mask register (rffidrfmr) this register defines the filter ma sk for the frame id rejection filter of the selected receive fifo. for details on frame id filtering see section 3.4.9.5, ?receive fifo filtering? . 3.3.2.59 receive fifo range filter configuration regi ster (rfrfcfr) this register provides access to the four internal fram e id range filter boundary registers of the selected receive fifo. for details on frame id range filter see section 3.4.9.5, ?receive fifo filtering? . 0x0096 write: poc:config 1514131211109876543210 r00000 fidrfmsk w reset0000000000000000 figure 3-57. receive fifo frame id rej ection filter mask register (rffidrfmr) table 3-68. rffidrfm r field descriptions field description 10?0 fidrfmsk frame id rejection filter mask ? filter mask for the frame id rejection filter. 0x0098 16-bit write access required write: wmd, ibd, sel: any time write: sid: poc:config 1514131211109876543210 r0 ibd sel 0 sid wwmd reset0000000000000000 figure 3-58. receive fifo range filter configuration register (rfrfcfr) table 3-69. rfrfcfr field descriptions field description 15 wmd write mode ? this control bit defines the write mode of this register. 0 write to all fields in this register on write access. 1 write to sel and ibd field only on write access. 14 ibd interval boundary ? this control bit selects the interval boundary to be programmed with the sid value. 0 program lower interval boundary 1 program upper interval boundary 13?12 sel filter selector ? this control field selects the frame id range filter to be accessed. 00 select frame id range filter 0. 01 select frame id range filter 1. 10 select frame id range filter 2. 11 select frame id range filter 3. 10?0 sid slot id ? defines the ibd-selected frame id boundary value for the sel-selected range filter. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 118 freescale semiconductor 3.3.2.60 receive fifo range filt er control regi ster (rfrfctr) this register is used to enable a nd disable each frame id range filter and to define whether it is running as acceptance or rejection filter. 3.3.2.61 last dynamic transmit sl ot channel a register (ldtxslar) 0x009a write: any time 1514131211109876543210 r0000 f3md f2md f1md f0md 0000 f3en f2en f1en f0en w reset0000000000000000 figure 3-59. receive fifo range fi lter control register (rfrfctr) table 3-70. rfrfctr field descriptions field description 11 f3md range filter 3 mode ? this control bit defines the filter mode of the frame id range filter 3. 0 range filter 3 runs as acceptance filter 1 range filter 3 runs as rejection filter 10 f2md range filter 2 mode ? this control bit defines the filter mode of the frame id range filter 2. 0 range filter 2 runs as acceptance filter 1 range filter 2 runs as rejection filter 9 f1md range filter 1 mode ? this control bit defines the filter mode of the frame id range filter 1. 0 range filter 1 runs as acceptance filter 1 range filter 1 runs as rejection filter 8 f0md range filter 0 mode ? this control bit defines the filter mode of the frame id range filter 0. 0 range filter 0 runs as acceptance filter 1 range filter 0 runs as rejection filter 3 f3en range filter 3 enable ? this control bit is used to enable and disable the frame id range filter 3. 0 range filter 3 disabled 1 range filter 3 enabled 2 f2en range filter 2 enable ? this control bit is used to enable and disable the frame id range filter 2. 0 range filter 2 disabled 1 range filter 2 enabled 1 f1en range filter 1 enable ? this control bit is used to enable and disable the frame id range filter 1. 0 range filter 1 disabled 1 range filter 1 enabled 0 f0en range filter 0 enable ? this control bit is used to enable and disable the frame id range filter 0. 0 range filter 0 disabled 1 range filter 0 enabled 0x009c 1514131211109876543210 r00000 lastdyntxslota w reset0000000000000000 figure 3-60. last dynamic slot channel a register (ldtxslar) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 119 this register provides the number of the last transmission slot in the dynamic segment for channel a. this register is updated after the end of the dynamic segment and before th e start of the next communication cycle. 3.3.2.62 last dynamic transmit sl ot channel b register (ldtxslbr) this register provides the number of the last transmission slot in the dy namic segment for channel b. this register is updated after the end of the dynamic segment and before th e start of the next communication cycle. 3.3.2.63 protocol configuration registers the following configurati on registers provide the necessary confi guration information to the protocol engine. the individual values in the registers are described in table 3-73 . for more details about the flexray related configuration parameters and the allowed parameter ranges, see flexray communications system protoc ol specification, version 2.1 . table 3-71. ldtxslar field descriptions field description 10?0 lastdyntx slota last dynamic transmission slot channel a ? protocol related variable: zlastdyntxslot channel a number of the last transmission slot in the dynamic se gment for channel a. if no frame was transmitted during the dynamic segment on channel a, the value of this field is set to 0. 0x009e 1514131211109876543210 r00000 lastdyntxslotb w reset0000000000000000 figure 3-61. last dynamic slot channel b register (ldtxslbr) table 3-72. ldtxslbr field descriptions field description 10?0 lastdyntx slotb last dynamic transmission slot channel b ? protocol related variable: zlastdyntxslot channel b number of the last transmission slot in the dynamic segm ent for channel b. if no frame was transmitted during the dynamic segment on channel b the value of this field is set to 0. table 3-73. protocol configuration register fields (sheet 1 of 3) name description 1 min max unit pcr coldstart_attempts gcoldstartattempts number 3 action_point_offset gdactionpointoffset - 1 mt 0 cas_rx_low_max gdcasrxlowmax - 1 gdbit 4 dynamic_slot_idle_phase gddynamicslotidlephase minislot 28 minislot_action_point_offset gdminislotactionpointoffset - 1 mt 3 minislot_after_action_point gdminislot - gdminislotactionpointoffset - 1 mt 2 static_slot_length gdstaticslot mt 0 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 120 freescale semiconductor static_slot_after_action_point gdstaticslot - gdactionpointoffset - 1 mt 13 symbol_window_exists gdsymbolwindow !=0 0 1 bool 9 symbol_window_after_action_point gdsymbolwindow - gdactionpointoffset - 1 mt 6 tss_transmitter gdtsstransmitter gdbit 5 wakeup_symbol_rx_idle gdwakeupsymbolrxidle gdbit 5 wakeup_symbol_rx_low gdwakeupsymbolrxlow gdbit 3 wakeup_symbol_rx_window gdwakeupsymbolrxwindow gdbit 4 wakeup_symbol_tx_idle gdwakeupsymboltxidle gdbit 8 wakeup_symbol_tx_low gdwakeupsymboltxlow gdbit 5 noise_listen_timeout ( glistennoise * pdlistentimeout ) - 1 t 16/17 macro_initial_offset_a pmacroinitialoffset[a] mt 6 macro_initial_offset_b pmacroinitialoffset[b] mt 16 macro_per_cycle gmacropercycle mt 10 macro_after_first_static_slot gmacropercycle - gdstaticslot mt 1 macro_after_offset_correction gmacropercycle - goffsetcorrectionstart mt 28 max_without_clock_correction_fatal gmaxwithoutclockcorrectionfatal cyclepairs 8 max_without_clock_ correction_passive gmaxwithoutclockcorrectionpassive cyclepairs 8 minislot_exists gnumberofminislots !=0 0 1 bool 9 minislots_max gnumberofminislots - 1 minislot 29 number_of_static_slots gnumberofstaticslots static slot 2 offset_correction_start goffsetcorrectionstart mt 11 payload_length_static gpayloadlengthstatic 2-bytes 19 max_payload_length_dynamic ppayloadlengthdynmax 2-bytes 24 first_minislot_action_point_offset max( gdactionpointoffset , gdminislotactionpointoffset ) - 1 mt 13 allow_halt_due_to_clock pallowhaltduetoclock bool 26 allow_passive_to_active pallowpassivetoactive cyclepairs 12 cluster_drift_damping pclusterdriftdamping t24 comp_accepted_startup_range_a pdacceptedstartuprange - pdelaycompensationcha t22 comp_accepted_startup_range_b pdacceptedstartuprange - pdelaycompensationchb t26 listen_timeout pdlistentimeout - 1 t 14/15 key_slot_id pkeyslotid number 18 key_slot_used_for_startup pkeyslotusedforstartup bool 11 key_slot_used_for_sync pkeyslotusedforsync bool 11 latest_tx gnumberofminislots - platesttx minislot 21 sync_node_max gsyncnodemax number 30 micro_initial_offset_a pmicroinitialoffset[a] t20 micro_initial_offset_b pmicroinitialoffset[b] t20 table 3-73. protocol configuration register fields (sheet 2 of 3) name description 1 min max unit pcr flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 121 3.3.2.63.1 protocol configur ation register 0 (pcr0) 3.3.2.63.2 protocol configur ation register 1 (pcr1) micro_per_cycle pmicropercycle t 22/23 micro_per_cycle_min pmicropercycle - pdmaxdrift t 24/25 micro_per_cycle_max pmicropercycle + pdmaxdrift t 26/27 micro_per_macro_nom_half round( pmicropermacronom / 2) t7 offset_correction_out poffsetcorrectionout t9 rate_correction_out pratecorrectionout t14 single_slot_enabled psingleslotenabled bool 10 wakeup_channel pwakeupchannel see ta bl e 3 - 7 4 10 wakeup_pattern pwakeuppattern number 18 decoding_correction_a pdecodingcorrection + pdelaycompensation[a] + 2 t19 decoding_correction_b pdecodingcorrection + pdelaycompensation[b] + 2 t7 key_slot_header_crc header crc for key slot 0x000 0x7ff number 12 extern_offset_correction pexternoffse tcorrection t29 extern_rate_correction pexternratecorrection t21 1 see flexray communications system protocol specification, version 2.1 for detailed protocol parameter definitions table 3-74. wakeup channel selection wakeup_channel wakeup channel 0a 1b 0x00a0 write: poc:config 1514131211109876543210 r action_point_offset st atic_slot_length w reset0000000000000000 figure 3-62. protocol configuration register 0 (pcr0) 0x00a2 write: poc:config 1514131211109876543210 r0 0 macro_after_first_static_slot w reset0000000000000000 figure 3-63. protocol configuration register 1 (pcr1) table 3-73. protocol configuration register fields (sheet 3 of 3) name description 1 min max unit pcr flexray module (flexrayv2) mfr4300 data sheet, rev. 3 122 freescale semiconductor 3.3.2.63.3 protocol configur ation register 2 (pcr2) 3.3.2.63.4 protocol configur ation register 3 (pcr3) 3.3.2.63.5 protocol configur ation register 4 (pcr4) 3.3.2.63.6 protocol configur ation register 5 (pcr5) 3.3.2.63.7 protocol configur ation register 6 (pcr6) 0x00a4 write: poc:config 1514131211109876543210 r minislot_after_action_point number_of_static_slots w reset0000000000000000 figure 3-64. protocol configuration register 2 (pcr2) 0x00a6 write: poc:config 1514131211109876543210 r wakeup_symbol_rx_low minislot_action_point_offset[4:0] coldstart_attempts w reset0000000000000000 figure 3-65. protocol configuration register 3 (pcr3) 0x00a8 write: poc:config 1514131211109876543210 r cas_rx_low_max wakeup_symbol_rx_window w reset0000000000000000 figure 3-66. protocol configuration register 4 (pcr4) 0x00aa write: poc:config 1514131211109876543210 r tss_transmitter wakeup_symbol_tx_low wakeup_symbol_rx_idle w reset0000000000000000 figure 3-67. protocol configuration register 5 (pcr5) 0x00ac write: poc:config 1514131211109876543210 r0 symbol_window_after_action_point macro_initial_offset_a w reset0000000000000000 figure 3-68. protocol configuration register 6 (pcr6) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 123 3.3.2.63.8 protocol configur ation register 7 (pcr7) 3.3.2.63.9 protocol configur ation register 8 (pcr8) 3.3.2.63.10 protocol configur ation register 9 (pcr9) 3.3.2.63.11 protocol configur ation register 10 (pcr10) 0x00ae write: poc:config 1514131211109876543210 r decoding_correction_b micro_per_macro_nom_half w reset0000000000000000 figure 3-69. protocol configuration register 7 (pcr7) 0x00b0 write: poc:config 1514131211109876543210 r max_without_clock_ correction_fatal max_without_clock_ correction_passive wakeup_symbol_tx_idle w reset0000000000000000 figure 3-70. protocol configuration register 8 (pcr8) 0x00b2 write: poc:config 1514131211109876543210 r mini slot_ exists sym bol_ win dow_ exists offset_correction_out w reset0000000000000000 figure 3-71. protocol configuration register 9 (pcr9) 0x00b4 write: poc:config 1514131211109876543210 r single _slot _en abled wake up_ chan nel macro_per_cycle w reset0000000000000000 figure 3-72. protocol confi guration register 10 (pcr10) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 124 freescale semiconductor 3.3.2.63.12 protocol configur ation register 11 (pcr11) 3.3.2.63.13 protocol configur ation register 12 (pcr12) 3.3.2.63.14 protocol configur ation register 13 (pcr13) 3.3.2.63.15 protocol configur ation register 14 (pcr14) 0x00b6 write: poc:config 1514131211109876543210 rkey_ slot_ used_ for_ start up key_ slot_ used_ for_ sync offset_correction_start w reset0000000000000000 figure 3-73. protocol confi guration register 11 (pcr11) 0x00b8 write: poc:config 1514131211109876543210 r allow_passive_to_active key_slot_header_crc w reset0000000000000000 figure 3-74. protocol confi guration register 12 (pcr12) 0x00ba write: poc:config 1514131211109876543210 r first_minislot_action_point_offset static_slot_after_action_point w reset0000000000000000 figure 3-75. protocol confi guration register 13 (pcr13) 0x00bc write: poc:config 1514131211109876543210 r rate_correction_out listen_timeout[20:16] w reset0000000000000000 figure 3-76. protocol confi guration register 14 (pcr14) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 125 3.3.2.63.16 protocol configur ation register 15 (pcr15) 3.3.2.63.17 protocol configur ation register 16 (pcr16) 3.3.2.63.18 protocol configur ation register 17 (pcr17) 3.3.2.63.19 protocol configur ation register 18 (pcr18) 3.3.2.63.20 protocol configur ation register 19 (pcr19) 0x00be write: poc:config 1514131211109876543210 r listen_timeout[15:0] w reset0000000000000000 figure 3-77. protocol confi guration register 15 (pcr15) 0x00c0 write: poc:config 1514131211109876543210 r macro_initial_offset_b no ise_listen_tim eout[24:16] w reset0000000000000000 figure 3-78. protocol confi guration register 16 (pcr16) 0x00c2 write: poc:config 1514131211109876543210 r noise_listen_timeout[15:0] w reset0000000000000000 figure 3-79. protocol confi guration register 17 (pcr17) 0x00c4 write: poc:config 1514131211109876543210 r wakeup_pattern key_slot_id w reset0000000000000000 figure 3-80. protocol confi guration register 18 (pcr18) 0x00c6 write: poc:config 1514131211109876543210 r decoding_correction_a payload_length_static w reset0000000000000000 figure 3-81. protocol confi guration register 19 (pcr19) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 126 freescale semiconductor 3.3.2.63.21 protocol configur ation register 20 (pcr20) 3.3.2.63.22 protocol configur ation register 21 (pcr21) 3.3.2.63.23 protocol configur ation register 22 (pcr22) 3.3.2.63.24 protocol configur ation register 23 (pcr23) 3.3.2.63.25 protocol configur ation register 24 (pcr24) 0x00c8 write: poc:config 1514131211109876543210 r micro_initial_offset_b micro_initial_offset_a w reset0000000000000000 figure 3-82. protocol confi guration register 20 (pcr20) 0x00ca write: poc:config 1514131211109876543210 r extern_rate_ correction latest_tx w reset0000000000000000 figure 3-83. protocol confi guration register 21 (pcr21) 0x00cc write: poc:config 1514131211109876543210 r r* comp_accepted_startup_range_a micro_per_cycle[19:16 w reset0000000000000000 figure 3-84. protocol confi guration register 22 (pcr22) 0x00ce write: poc:config 1514131211109876543210 r micro_per_cycle[15:0] w reset0000000000000000 figure 3-85. protocol confi guration register 23 (pcr23) 0x00d0 write: poc:config 1514131211109876543210 r cluster_drift_damping max_payload_length_dynamic micro_per_cycle_min [19:16] w reset0000000000000000 figure 3-86. protocol confi guration register 24 (pcr24) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 127 3.3.2.63.26 protocol configur ation register 25 (pcr25) 3.3.2.63.27 protocol configur ation register 26 (pcr26) 3.3.2.63.28 protocol configur ation register 27 (pcr27) 3.3.2.63.29 protocol configur ation register 28 (pcr28) 0x00d2 write: poc:config 1514131211109876543210 r micro_per_cycle_min[15:0] w reset0000000000000000 figure 3-87. protocol confi guration register 25 (pcr25) 0x00d4 write: poc:config 1514131211109876543210 r allow _halt_ due _to_ clock comp_accepted_startup_range_b micro_per_cycle_max [19:16] w reset0000000000000000 figure 3-88. protocol confi guration register 26 (pcr26) 0x00d6 write: poc:config 1514131211109876543210 r micro_per_cycle_max[15:0] w reset0000000000000000 figure 3-89. protocol confi guration register 27 (pcr27) 0x00d8 write: poc:config 1514131211109876543210 r dynamic_slot _idle_phase macro_after_offset_correction w reset0000000000000000 figure 3-90. protocol confi guration register 28 (pcr28) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 128 freescale semiconductor 3.3.2.63.30 protocol configur ation register 29 (pcr29) 3.3.2.63.31 protocol configur ation register 30 (pcr30) 3.3.2.64 message buffer configuration, control, status registers (mbccsrn) the content of these registers comprises message buf fer configuration data, me ssage buffer control data, message buffer status information, and message buffer interrupt flags. 0x00da write: poc:config 1514131211109876543210 r extern_offset_ correction minislots_max w reset0000000000000000 figure 3-91. protocol confi guration register 29 (pcr29) 0x00dc write: poc:config 1514131211109876543210 r000000000000 sync_node_max w reset0000000000000000 figure 3-92. protocol configuration register 30 (pcr30) module base + 0x0100, 0x0108,..., 0x04f8 write: mcm, mbt, mtd: poc:config or mb_dis write: cmt: mb_lck write: edt, lckt, mbie, mbif: normal mode additional reset: cmt, dup, dval, mbif: message buffer disable 1514131211109876543210 r0 mcm mbt mtd cmt 00 mbie 0 0 0 dup dval eds lcks mbif w edt lckt reset0000000000000000 figure 3-93. message buffer configurati on, control, status registers (mbccsrn) table 3-75. mbccsrn field descriptions (sheet 1 of 3) field description message buffer configuration 14 mcm message buffer commit mode ? this bit applies only to double buffered transmit message buffers and defines the commit mode. 0 streaming commit mode 1 immediate commit mode 13 mbt message buffer type ? this bit applies only to transmit message buffers and defines the buffering type. 0 single buffered transmit message buffer 1 double buffered transmit message buffer 12 mtd message buffer transfer direction ? this bit defines the transfer direction of the message buffer. 0 receive message buffer 1 transmit message buffer flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 129 message buffer control 11 cmt commit for transmission ? this bit applies only to transmit message buffers and indicates whether the message buffer contains valid data that are ready for transmission. both the application and the flexray module can modify this bit. ? application: the application sets this bit to indicate that the transmit message buff er contains valid data ready for transmission. the application clears this bit to indica te that the message buffer data are no longer valid for transmission. ? flexray module: the flexray module clears this bi t when the message buffer data are no longer valid for transmission. 0 message buffer does not contain valid data. 1 message buffer contains valid data. 10 edt enable/disable trigger ? this trigger bit is used to enable and disable a message buffer. the message buffer enable is triggered when the application writes ?1? to th is bit and the message buffer is disabled, i.e. the eds status bit is ?0?. the message buffer disable is triggered when the application writes ?1? to this bit and the message buffer is enabled, i.e. the eds status bit is ?1?. 0 no effect 1 message buffer enable/disable triggered note: if the application writes ?1? to this bit, the write access to all other bits is ignored. 9 lckt lock/unlock trigger ? this trigger bit is used to lock and unlock a message buffer. the message buffer lock is triggered when the application writes ?1? to this bit and t he message buffer is not locked, i.e. the lcks status bit is ?0?. the message buffer unlock is triggered when the appl ication writes ?1? to this bit and the message buffer is locked, i.e. the lcks status bit is ?1?. 0 no effect 1 trigger message buffer lock/unlock note: if the application writes ?1? to this bit and ?0? to the edt bit, the write access to all other bits is ignored. 8 mbie message buffer interrupt enable ? this control bit defines whether the message buffer will generate an interrupt request when its mbif flag is set. 0 interrupt request generation disabled 1 interrupt request generation enabled message buffer status 4 dup data updated ? this status bit applies only to receive message buffers. it is always ?0? for transmit message buffers. this bit provides information whether the frame header in the message buffer header field and the message buffer data field were updated. see section 3.4.6.3.4, ?message buffer status update ? for a detailed description of the update condtions. 0 frame header and message buffer data field not updated. 1 frame header and message buffer data field updated. 3 dval data valid ? the semantic of this status bit depends on the message buffer type and transfer direction. ? receive message buffer: indicates whether the message buffer da ta field contains valid frame data. see section 3.4.6.3.4 , ?message buffer status update ? for a detailed update description of the update conditions. 0 message buffer data field contains no valid frame data 1 message buffer data field contains valid frame data ? single transmit message buffer : indicates whether the message is transferred again due to the state transmission mode of the message buffer. 0 message transferred for the first time. 1 message will be transferred again. ? double transmit message buffer : for the commit side it is always ?0?. for the transmit side it indicates whether the message is transferred again due to the state transmission mode of the message buffer. 0 message transferred for the first time. 1 message will be transferred again. table 3-75. mbccsrn field descriptions (sheet 2 of 3) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 130 freescale semiconductor 3.3.2.65 message buffer cycle counter filter registers (mbccfrn) this register contains message buffer configurat ion data for the transm ission mode, the channel assignment, and for the cycle counter filtering. for detailed information on cycle c ounter filtering, refer to section 3.4.7.1.2, ?message buffer cycle counter filtering? . 2 eds enable/disable status ? this status bit indicates whether the message buffer is enabled or disabled. 0 message buffer is disabled. 1 message buffer is enabled. 1 lcks lock status ? this status bit indicates the current lock status of the message buffer. 0 message buffer is not locked by the application. 1 message buffer is locked by the application. 0 mbif message buffer interrupt flag ? the semantic of this flag depends on the message buffer transfer direction. ? receive message buffer: this flag is set when the slot status in the message buffer header field was updated and this slot was not an empty dynamic slot. see section 3.4.6.3.4, ?message buffer status update? for a detailed description of the update conditions. 0 slot status not updated 1 slot status updated and slot was not an empty dynamic slot ? transmit message buffer: this flag is set when the slot status in the message buffer header field was updated. additionally this flag is set immediately when a transmit message buffer was enabled. 0 slot status not updated 1 slot status updated / message buffer just enabled writing a '1' clears this flag. writ ing a ?0? will not change the flag state. 0x0102, 0x010a,..., 0x04fa write: poc:config or mb_dis 1514131211109876543210 r mtm cha chb ccfe ccfmsk ccfval w reset bits located in physical memory, no t affected by reset, no reset value figure 3-94. message buffer cycle counter filter registers (mbccfrn) table 3-76. mbccfrn field descriptions field description 15 mtm message buffer transmission mode ? this control bit applies only to transmit message buffers and defines the transmission mode. 0 event transmission mode 1 state transmission mode 14?13 cha chb channel assignment ? these control bits define the channel assignment and control the receive and transmit behavior of the message buffer according to table 3-77 . 12 ccfe cycle counter filtering enable ? this control bit is used to enable and disable the cycle counter filtering. 0 cycle counter filtering disabled 1 cycle counter filtering enabled 11?6 ccfmsk cycle counter filtering mask ? this field defines the filter mask for the cycle counter filtering. 5?0 ccfval cycle counter filtering value ? this field defines the filter value for the cycle counter filtering. table 3-75. mbccsrn field descriptions (sheet 3 of 3) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 131 . note if at least one message buffer assigned to a certain slot is assigned to both channels, then all message buffers assigne d to this slot have to be assigned to both channels. otherwis e, the message buffer configuration is illegal and the result of the message buf fer search is not defined. 3.3.2.66 message buffer frame id registers (mbfidrn) table 3-77. channel assignment description cha chb transmit message buffer receive message buffer static segment dynamic segment static segment dynamic segment 1 1 transmit on both channel a and channel b transmit on channel a only store first valid frame received on either channel a or channel b store first valid frame received on channel a, ignore channel b 0 1 transmit on channel b transmit on channel b store first valid frame received on channel b store first valid frame received on channel b 1 0 transmit on channel a transmit on channel a store first valid frame received on channel a store first valid frame received on channel a 0 0 no frame transmission no frame transmission no frame stored no frame stored 0x0104, 0x010c,..., 0x04fc write: poc:config or mb_dis 1514131211109876543210 r00000 fid w reset00000 bits located in physical memory, not affected by reset, no reset value figure 3-95. message buffer frame id registers (mbfidrn) table 3-78. mbfidrn field descriptions field description 10?0 fid frame id ? the semantic of this field depends on the message buffer transfer type. for receive message buffers it is used as a filter value to determine whether or not the message buffer is used for reception of a message received in a slot with the slot id equal to fid. for a transmit message buffer it is used to determine the slot in which the message in this message buffer will be transmitted. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 132 freescale semiconductor 3.3.2.67 message buffer index registers (mbidxrn) 0x0106, 0x010e,..., 0x04fe write: poc:config or mb_dis 1514131211109876543210 r00000000 mbidx w reset 00000000 bits located in physical memory, not affected by reset, no reset value figure 3-96. message buffer index registers (mbidxrn) table 3-79. mbidxrn field descriptions field description 7?0 mbidx message buffer index ? this field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer. the application writes the index of the initially associated message buffer header field into this register. the flexray module updates this register after frame reception or transmission. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 133 3.4 functional description this section provides a detailed description of the functionality implemented in the flexray module. 3.4.1 message buffer concept the flexray module uses a data structure called message buffer to store frame data, configuration, control, and status data. each message buf fer consists of two parts, the message buffer control data and the physical message buffer. the message buffer control data are located in dedicated registers. the structure of the message buffer control data depends on the message buffer type and is described in section 3.4.3, ?message buffer types ?. the physical message buffer is locat ed in the frm and is described in section 3.4.2, ?physical message buffer ?. 3.4.2 physical message buffer all flexray messages and related fram e and slot status information of r eceived frames and of frames to be transmitted to the flexray bus ar e stored in data structures called physical message buffers . the physical message buffers are located in the frm.the structure of a physi cal message buffer is depicted in figure 3-97 . a physical message buffer cons ists of two fields, the message buffer header field and the message buffer data field . the message buffer header field contains the frame header , the data field offset , and the slot status .the message buffer data field contains the frame data . the connection between the two fields is established by the data field offset . figure 3-97. physical message buffer structure 3.4.2.1 message buffer header field the message buffer header field is a contiguous region in the frm and occupies te n bytes. it contains the frame header, the data field offset, and th e slot status. its structure is shown in figure 3-97 . the physical start address sadr_mbhf of the message buffer header field must be 16-bit aligned. 3.4.2.1.1 frame header the frame header occupies the first six bytes in the message buffer header field. it contains all flexray frame header related information according to the flexray communications system protocol data field offset frame data message buffer header field message buffer data field sadr_mbdf sadr_mbhf slot status frame header frm flexray module (flexrayv2) mfr4300 data sheet, rev. 3 134 freescale semiconductor specification, version 2.1 . a detailed description of the usage a nd the content of the frame header is provided in section 3.4.5.2.1, ?frame head er section description? . 3.4.2.1.2 data field offset the data field offset follows the fr ame header in the message buffer data field and occupies two bytes. it contains the offset of the corres ponding message buffer data field with respect to the flexray module frm base address 0x800. the data field offset is used to determine the start address sadr_mbdf of the corresponding message buffer data field in the frm according to equation 3-1 . sadr_mbdf = [data field offset] + 0x800 eqn. 3-1 3.4.2.1.3 slot status the slot status occupies the last two bytes of the me ssage buffer header field. it provides the slot and frame status related informat ion according to the flexray communications syst em protocol specification, version 2.1 . a detailed description of the content and usage of the slot status is provided in section 3.4.5.2.3, ?slot status description? . 3.4.2.2 message buffer data field the message buffer data fiel d is a contiguous area of 2- byte entities. this field c ontains the frame payload data, or a part of it, of the frame to be transmit ted to or received from th e flexray bus. the minimum length of this field depends on the specific message buf fer configuration and is specified in the message buffer descriptions given in section 3.4.3, ?message buffer types ?. 3.4.3 message buffer types the flexray module provides three di fferent types of message buffers. ? individual message buffers ? receive shadow buffers ? receive fifo buffers for each message buffer type the st ructure of the physical message buffe r is identical. the message buffer types differ only in the structure and content of message buffer contro l data, which control the related physical message buffer. the message buffer control data are descri bed in the following sections. 3.4.3.1 individual message buffers the individual message buffers are used for all t ypes of frame transmission and for dedicated frame reception based on individual filter settings for each message buffer. the flexray module supports three types of individual message buf fers, which are described in section 3.4.6, ?individua l message buffer functional description ?. each individual message buffer consists of two parts, the phys ical message buffer, which is located in the frm, and the message buffer control data, which are lo cated in dedicated registers. the structure of an individual message buffer is given in figure 3-98 . flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 135 each individual message buffer has a message buffe r number n assigned, which determines the set of message buffer control registers a ssociated to this individual messa ge buffer. the individual message buffer with message buffer number n is controlled by the regist ers mbccsrn, mbccfrn, mbfidrn, and mbidxrn. the connection between the message buffer control registers and the physical message buffer is established by the message buffe r index field mbidx in the message buffer index registers (mbidxrn) . the start address sadr_mbhf of the related messag e buffer header field in the frm is determined according to equation 3-2 . sadr_mbhf = (mbidxrn.mbidx * 10) + 0x800 eqn. 3-2 figure 3-98. individual message buffer structure 3.4.3.1.1 individual message buffer segments the set of the individual message buffers can be sp lit up into two message buffer segments using the message buffer segment size and utilization register (mbssutr) . all individual message buffers with a message buffer number n <= mbssu tr.last_mb_seg1 belong to the first message buffer segment. all individual message buffers with a message buffer number n > mbssutr.last_mb_seg1 belong to the second message buffer segment. the following rules apply to the length of the message buffer data field: ? all physical message buffers associated to indi vidual message buffers that belong to the same message buffer segment must have message buffer data fields of the same length ? the minimum length of the message buffer data fi eld for individual messag e buffers in the first message buffer segment is 2 * mbdsr.mbseg1ds bytes ? the minimum length of the messag e buffer data field fo r individual message buf fers assigned to the second segment is 2 * mbdsr.mbseg2ds bytes. mbfidrn message buffer control registers mbccsrn mbccfrn mbidxrn >= mbdsr.mbseg[1,2] * 2 bytes framedata frame header slot status data field offset sadr_mbdf message buffer data field message buffer header field sadr_mbhf frm flexray module (flexrayv2) mfr4300 data sheet, rev. 3 136 freescale semiconductor 3.4.3.2 receive shadow buffers the receive shadow buffers are required for the fram e reception process for individual message buffers. the flexray module provides four receive shadow buffe rs, one receive shadow buffer per channel and per message buffer segment. each receive shadow buffer consists of two parts, th e physical message buffer lo cated in the frm and the receive shadow buffer control regist ers located in dedicated registers. the structure of a receive shadow buffer is shown in figure 3-99 . the four internal shadow buffer c ontrol registers can be accessed by the receive shadow buffer index register (rsbir) . the connection between the receive sh adow buffer control register and the physical message buffer for the selected receive shadow buffer is established by th e receive shadow buffer i ndex field rsbidx in the receive shadow buffer index register (rsbir) . the start address sadr_mbh f of the related message buffer header field in the fr m is determined according to equation 3-3 . sadr_mbhf = (rsbir.rsbidx * 10) + 0x800 eqn. 3-3 the length required for the message buffer data fiel d depends on the message buffer segment that the receive shadow buffer is assigned to. for the receive shadow buffers assigned to the first message buffer segment, the length must be the same as for the i ndividual message buffers assi gned to the first message buffer segment. for the receive sha dow buffers assigned to the second message buffe r segment, the length must be the same as for the indi vidual message buffers assigned to the second message buffer segment. the receive shadow buffer assignment is described in receive shadow buffer index register (rsbir) . figure 3-99. receive shadow buffer structure 3.4.3.3 receive fifo the receive fifo implements a fr ame reception system based on the fifo concept. the flexray module provides two independent recei ve fifos, one per channel. rsbidx_3 rsbidx_2 rsbidx_1 receive shadow buffer control register rsbidx_0 frm >= mbdsr.mbseg[1,2] * 2 bytes frame data frame header slot status data field offset sadr_mbdf message buffer data field message buffer header field sadr_mbhf flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 137 a receive fifo consists of a set of physical message buffers in th e frm and a set of receive fifo control registers located in dedicated registers. th e structure of a receive fifo is given in figure 3-100 . the connection between the receive fifo control registers and the se t of physical message buffers is established by the start index field sidx in the receive fifo start i ndex register (rfsir) , the fifo depth field fifo_depth in the receive fifo depth and size register (rfdsr) , and the read index field rdidx receive fifo a read index register (rfarir) / receive fifo b read index register (rfbrir) . the start address sadr_mbhf_1 of the first me ssage buffer header field that belongs to the receive fifo in the frm is determined according to equation 3-4 . sadr_mbhf_1 = (rfsir.sidx * 10) + 0x800 eqn. 3-4 the start address sadr_mbhf_n of th e last message buffer header field that belongs to the receive fifo in the frm is determined according to equation 3-5 . sadr_mbhf_n = ((rfsir.sidx+rfdsr.fifo_depth) * 10) + 0x800 eqn. 3-5 note all message buffer header fields assigned to a receive fifo must be a contiguous region. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 138 freescale semiconductor figure 3-100. receive fifo structure 3.4.3.4 message buffer conf iguration and control data this section describes the configuration and control data for each message buffer type. 3.4.3.4.1 individual message buffer configuration data before an individual message buffer can be used for transmission or reception, it must be configured. there is a set of common configuratio n parameters that applies to all in dividual message buffers and a set of configuration parameters that applie s to each message buffer individually. common configuration data the set of common configurat ion data for indivi dual message buffers is located in the following registers. rfarir rfsir rfdsr rfarir rfdsr rfsir frame header 1 slot status 1 data field offset 1 framedata n receive fifo control register frm message buffer header fields message buffer data fields framedata 1 frame header n slot status n data field offset n >= rfdsr.entry_size * 2 bytes rfdsr.fifo_depth rfdsr.fifo_depth + frame header i slot status i data field offset i framedata i sadr_mbhf_1 sadr_mbhf_i sadr_mbhf_n sadr_mbdf_n sadr_mbdf_i sadr_mbdf_1 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 139 ? message buffer data size register (mbdsr) the mbseg2ds and mbseg1ds fields define the mini mum length of the message buffer data field with respect to the message buffer segment. ? message buffer segment size and utilization register (mbssutr) the last_mb_seg1 and last_mb_ util fields define the segm entation of the individual message buffers and the number of individual message buffers that are used. for more details, see section 3.4.3.1.1, ?individual message buffer segments ? specific configuration data the set of message buffer specific configuration data for individual me ssage buffers is located in the following registers. ? message buffer configuration, cont rol, status registers (mbccsrn) the mcm, mbt, mtd bits conf igure the message buffer type. ? message buffer cycle counter filter registers (mbccfrn) the mtm, cha, chb bits configure the transm ission mode and the channel assignment. the ccfe, ccfmsk, and ccfval bits and fiel ds configure the cycle counter filter. ? message buffer frame id registers (mbfidrn) for a transmit message buffer, the fid field is used to determine the slot in which the message in this message buffer will be transmitted. ? message buffer inde x registers (mbidxrn) this mbidx field provides the index of the mess age buffer header field of the physical message buffer that is currently associat ed with this message buffer. 3.4.3.5 individual message buffer control data during normal operation, each individua l message buffer can be controlled by the control and trigger bits cmt, lckt, edt, and mbie in the message buffer configuration, control, status registers (mbccsrn) . 3.4.3.6 receive shadow buffer configuration data before frame reception into the indi vidual message buffers can be perf ormed, the receive shadow buffers must be configured. the configur ation data are provided by the receive shadow buffer index register (rsbir) . for each receive shadow buffer, the application provides the mess age buffer header index. when the protocol is in the poc:normal active or poc:normal passive state, the receive shadow buffers are under full flexray module control. 3.4.3.7 receive fifo cont rol and configuration data this section describes the configuration a nd control data for the two receive fifos. 3.4.3.7.1 receive fifo configuration data the flexray module provides two completely independe nt receive fifos, one per channel. each fifo has its own set of configuration da ta. the configuration data are lo cated in the following registers: flexray module (flexrayv2) mfr4300 data sheet, rev. 3 140 freescale semiconductor ? receive fifo start i ndex register (rfsir) ? receive fifo depth and size register (rfdsr) ? receive fifo message id acceptance filter valu e register (rfmidafvr) ? receive fifo message id acceptance filter mask register (rfmiafmr) ? receive fifo frame id rejection filter value register (rffidrfvr) ? receive fifo frame id rejection filter mask register (rffidrfmr) ? receive fifo range filter conf iguration register (rfrfcfr) 3.4.3.7.2 receive fifo control data the application can access the re ceive fifo at any time usi ng the values provided in the receive fifo a read index register (rfarir) and receive fifo b read index register (rfbrir) . to update the receive fifo a read i ndex register (rfarir) , the application must write ?1? to the fifo a not empty interrupt flag fneaif in the global interrupt flag and enable register (gifer) . to update the receive fifo b read index register (rfbrir) the application must write ?1? to the fifo b not empty interrupt flag fnebif in the global interrupt flag and enable register (gifer) . each update increments the related read index. if the r ead index has reached the last fifo entry, it wraps back to the fifo start index. note the read index is increm ented or wrapped on each update, even if the fifo is empty. the update of an empty fifo results in an non-empty fifo and the fifo non-empty fifo is set to ?1?. 3.4.4 flexray memory layout the flexray module supports a wide ra nge of possible layouts for the frm. figure 3-101 shows an example layout. the followi ng set of rules applies to the layout of the frm: ? the frm is a contiguous region. ? the maximum size of the frm is 6 kbytes. ? the frm starts at address 0x800. the frm contains three areas: the message buffer header area , the message buffer data area , and the sync frame table area . the areas are described in this section. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 141 figure 3-101. example of frm layout 3.4.4.1 message buffer header area the message buffer header area contains all message buffer header fields of th e physical message buffers for all message buffer types. the following rules apply to the message buffer header fields for the three type of message buffers. 1. the start address sadr_mbhf of each message buffer header field for individual message buffers and receive shadow buffers must fulfill equation 3-6 . sadr_mbhf = (i * 10) + 0x800; (0 <= i <132) eqn. 3-6 2. the start address sadr_mbhf of each message buffer header field for the receive fifo must fulfill equation 3-7 . sadr_mbhf = (i * 10) + 0x800; (0 <= i < 1024) eqn. 3-7 3. the message buffer header fi elds for a receive fifo ha ve to be a contiguous area. 3.4.4.2 message buffer data area the message buffer data area contai ns all the message buffer data fiel ds of the physical message buffers. each message buffer data fiel d must start at a 16-bit boundary. message buffer header area frm message buffer data area sync frame table area data field offset frame header slot status data field offset frame header slot status message buffer header fields individual message buffers receive shadow buffers data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo a data field offset frame header slot status data field offset frame header slot status message buffer header fields receive fifo b data field offset frame header slot status 10 bytes 0x800 device memory flexray module (flexrayv2) mfr4300 data sheet, rev. 3 142 freescale semiconductor 3.4.4.3 sync frame table area the sync frame table area is used to provide a copy of the internal s ync frame tables for application access. refer to section 3.4.12, ?sync frame id and sync frame deviation tables ? for the description of the sync frame table area. 3.4.5 physical message buffer description this section provides a detailed de scription of the usage and the cont ent of the two parts of a physical message buffer, the message buffer header field and the message buffer data field. 3.4.5.1 message buffer prot ection and data consistency the physical message buffers are located in the frm. the flexra y module provides no means to protect the frm from uncontrolled or illegal host or other client write access. to ensure data consistency of the physical message buffers, the applic ation must follow the write access scheme that is given in the description of each of the p hysical message buffer fields. 3.4.5.2 message buffer header field description this section provides a detailed desc ription of the usage and content of the message buffer header field. a description of the structur e of the message buffer header fields is given in section 3.4.2.1, ?message buffer header field ?. each message buffer header fi eld consists of three sections: the frame header section, the data field offset, and the slot st atus section. for a detailed descript ion of the data field offset, see section 3.4.2.1.2, ?data field offset ?. 3.4.5.2.1 frame header section description frame header section content the semantic and content of the frame header section depends on the message buffer type. for individual receive message buffers and receive fifos, the frame header receives the frame header data of the first valid frame received on the assigned channels. if a receive message buffer is assigned to both channels, the first valid frame received on either channel a or channel b is stored. for receive shadow buffers, the frame header receives the frame header data of the current frame received regardless of whether th e frame is valid or not. for single and double transmit message buffers, the applicat ion writes the fr ame header of th e frame to be transmitted into this location. the frame header will be read out when the frame is transferred to the flexray bus. the structure of the frame header in the message buffer header field is given in figure 3-102 . a detailed description of the frame header fields is given in table 3-81 . flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 143 figure 3-102. frame header structure frame header section access the frame header is located in the frm. to ensure da ta consistency, the applica tion must follow the write access scheme described below. for receive message buffers, receive shadow buffers, a nd receive fifos, the application must not write to the frame header field. for transmit message buffers, th e application must follow the wr ite access restrictions given in table 3-80 . this table shows the condition under which the application can write to the frame header entries. in general, the application can modify all frame header entries when th e protocol is in the poc:config state or when the message buffer is disabled. for mess age buffers assigned to the dynamic segment, the application can modify all frame header entries excep t the frame id when the message buffer is locked. the frame header entries nuf, syf, suf, and cyccnt are not used for frame transmission. these values are generated internally before frame transmi ssion depending on the current transmission state and configuration. for transmit message buffers assigned to the static segment, the pldlen value must be equal to the value of the payload_length_static field in the protocol configurati on register 19 (pcr19) . if this is not fulfilled, the static payload length error flag spl_ef in the chi error flag register (chierfr) is set when the message buffer is under transmission. the pe generates a syntactically and semantically correct frame with payload_length_s tatic payload words and the payload lengt h field in the frame header set to payload_length_static. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0 r* ppi nuf syf suf fid 0x2 cyccnt pldlen 0x4 hdcrc = not used for tx message buffers, not updated for rx message buffers table 3-80. frame header write access constraints field tx single buffered double buffered static segment dynamic segment static segment dynamic segment commit side transmit side commit side transmit side fid poc:config or mb_dis r*, ppi nuf, syf suf cyccnt pldlen hdcrd poc:config or mb_dis poc:config or mb_dis or mb_lck poc:config or mb_dis poc:config or mb_dis or mb_lck poc:config or mb_dis flexray module (flexrayv2) mfr4300 data sheet, rev. 3 144 freescale semiconductor for transmit message buffers assigned to the dynamic segment, the pldlen value must be less than or equal to the value of the max_pa yload_length_dynamic field in the protocol configuration register 24 (pcr24) . if this is not fulfilled, the dynamic payload length error flag dpl_ef in the chi error flag register (chierfr) is set when the message buffer is under transmission. the pe generates a syntactically and semantically correct dynamic frame with pldlen payload words and the payload length field in the frame header set to pldlen. table 3-81. frame header field descriptions field description r* reserved bit ? this bit corresponds to the reserved bit in the flexray frame header. ? for receive and fifo message buffers, this is a stat us bit and represents the value of the reserved bit in the frame received on the flexray bus in the corresponding slot. ? for transmit message buffers, this is a control bit. the flexray module transmits this within the frame header. note: for protocol compliant operation, this control bit must be set to ?0? for transmit message buffers. ppi payload preamble indicator ? this bit corresponds to the payload preamble indicator in the flexray frame header. ? for receive and fifo message buffers, this is a status bit and repr esents the value of the payload preamble indicator of the first valid frame received on the flexray in the slot indicated by the cyccnt field. ? for transmit message buffers, this is a control bit. the flexray module uses this value to set the payload preamble indicator in the frame header of the frame to transmit. 0 no network management vector or message id in frame payload data 1 static segment: frame payload data contains network management vector dynamic segment: frame payload data contains message id nuf null frame indicator ? this bit corresponds to the null frame indicator in the flexray frame header. ? for receive message buffers and receive fifos, th is is a status bit and re presents the value of the null frame indicator of the first valid frame received on the flexray bus in the slot indicated by the cyccnt field. ? for transmit message buffers, the value of this bit is ignored. the flexray module determines internally whether a null frame or non-null frame must be transmitted and sets the null frame indicator accordingly. 0 null frame received 1 normal frame received syf sync frame indicator ? this bit corresponds to the sync frame indicator in the flexray frame header. ? for receive message buffers and receive fifos, this is a status bit and represents the value of the sync frame indicator of the first valid frame received on the flexray bus in the slot indicated by the cyccnt field. ? for transmit message buffers, the value of this bit is ignored. the flexray module determines internally whether a sync frame must be transmitted and sets the sync frame indicator accordingly. suf startup frame indicator ? this bit corresponds to the startup frame indicator in the flexray frame header. ? for receive message buffers and receive fifos, this is a status bit and represents the value of the startup frame indicator of the first valid frame received on the flexray bus in the slot indicated by the cyccnt field ? for transmit message buffers, the value of this bit is ignored. the flexray module determines internally whether a startup frame must be transmitted and sets the startup frame indicator accordingly. fid frame id ? for receive message buffers and receive fi fos, this field provides the value of the frame id field of the first valid frame received on the flexray bus in the slot indicated by the cyccnt field. ? for transmit message buffers, this field provides the value that will be transmitted in the frame id field of the flexray frame. note: for transmit message buffers, the application must program this field to the same value as in the corresponding message buffer frame id registers (mbfidrn) . if the flexray module detects a mismatch while transmitting the frame header, it will set the frame id error flag fid_ef in the chi error flag register (chierfr) . the value of the fid field will be ignored and replaced by the value provided in the message buffer frame id registers (mbfidrn) . flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 145 3.4.5.2.2 data field offset description data field offset content for a detailed description of the data field offset, see section 3.4.2.1.2, ?data field offset ?. data field offset access the application shall program the da ta field offset when configuring the message buffers either in the poc:config state or when the message buffer is disabled. 3.4.5.2.3 slot st atus description the slot status is a read-only structure for the a pplication and a write-only structure for the flexray module. the meaning and content of the slot status in the message buffer header field depends on the message buffer type. receive message buffer and receiv e fifo slot st atus description this section describes the slot st atus structure for the individual re ceive message buffers and receive fifos. the content of the slot st atus structure for receive message buffers depends on the message buffer type and on the channel assignment for indivi dual receive message buffers as given by table 3-82 . cyccnt cycle count ? for receive message buffer and receive fifos, this fi eld provides the number of the communication cycle in which the frame stored in this message buffer was received. ? for transmit message buffers, the value of this field is ignored. the flexray module will overwrite this value with the current cycle count valu e when it transmits the frame. pldlen payload length in 16-bit units ? for receive message buffers and receive fifos, this field provides the value of the payload length field of the first valid frame received on the flexray bu s in the slot indicated by the fid field. ? for transmit message buffers assigned to the static s egment, this value is ignored for the frame generation. the flexray module uses the value in the pcr19.paylaod_length_static to set the value of the payload length field in the transmitted frame. ? for transmit message buffers assigned to the dynamic s egment, this value is used to set the value of the payload length field in the tr ansmitted frame. note: the value of this field is given in numbers of 16-bit units hdcrc header crc ? for receive and fifo message buffers, this field provides the value of the header crc of the received frame. ? for transmit message buffers, this field provides the header crc value as it was given by the application.the flexray module transmits this value in the header crc field of the transmitted frame. table 3-81. frame header field descriptions (continued) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 146 freescale semiconductor the meaning of the bits in the slot status structure is explained in table 3-83 . figure 3-103. receive message buffer slot status structure (chab) figure 3-104. receive message buffer slot status structure (cha) figure 3-105. receive message buffer slot status structure (chb) table 3-82. receive message buffer slot status content receive message buffer ty pe slot status content individual receive message buffer assigned to both channels mbccsrn.cha=?1? and mbccsrn.chb=?1? see figure 3-103 individual receive message buffer assigned to channel a mbccsrn.cha=?1? and mbccsrn.chb=?0? see figure 3-104 individual receive message buffer assigned to channel b mbccsrn.cha=?0? and mbccsrn.chb=?1? see figure 3-105 receive fifo channel a message buffer see figure 3-104 receive fifo channel b message buffer see figure 3-105 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r vfb syb nfb sub seb ceb bvb ch vfa sya nfa sua sea cea bva 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 vfa sya nfa sua sea cea bva 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r vfb syb nfb sub seb ceb bvb 1 0 0 0 0 0 0 0 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 3-83. receive message buffer slot status field descriptions field description common message buffer status bits 15 vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = ?0? 1 vss!validframe = ?1? 14 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = ?0? 1 vrf!header!syfindicator = ?1? 13 nfb null frame indi cator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = ?0? 1 vrf!header!nfindicator = ?1? 12 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = ?0? 1 vrf!header!sufindicator = ?1? flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 147 transmit message buffer slot status description this section describes the slot status structure for transmit message buffers. on ly the tca and tcb status bits are directly related to the tran smission process. all other status bits in this structure are related to a receive process that may have occu rred. the content of the slot stat us structure for transmit message buffers depends on the channel assignment as given by table 3-84 . 11 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = ?0? 1 vss!syntaxerror = ?1? 10 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = ?0? 1 vss!contenterror = ?1? 9 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = ?0? 1 vss!bviolation = ?1? 8 ch channel first valid received ? this status bit applies only to receive message buffers assigned to the static segment and to both channels. it indica tes the channel that has received the first valid frame in the slot. this flag is set to ?0? if no valid frame was received at all in the subscribed slot. 0 first valid frame received on channel a, or no valid frame received at all 0 first valid frame received on channel b 7 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = ?0? 1 vss!validframe = ?1? 6 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = ?0? 1 vrf!header!syfindicator = ?1? 5 nfa null frame indi cator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = ?0? 1 vrf!header!nfindicator = ?1? 4 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = ?0? 1 vrf!header!sufindicator = ?1? 3 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = ?0? 1 vss!syntaxerror = ?1? 2 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = ?0? 1 vss!contenterror = ?1? 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = ?0? 1 vss!bviolation = ?1? table 3-83. receive message buffer slot status field descriptions (continued) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 148 freescale semiconductor the meaning of the bits in the slot status structure is described in table 3-83 . figure 3-106. transmit message buffer slot status structure (chab) figure 3-107. transmit message buffer slot status structure (cha) figure 3-108. transmit message buffer slot status structure (chb) table 3-84. transmit message buffer slot status content transmit message buffer type slot status content individual transmit message buffer assigned to both channels mbccsrn.cha=?1? and mbccsrn.chb=?1? see figure 3-106 individual transmit message buffer assigned to channel a mbccsrn.cha=?1? and mbccsrn.chb=?0? see figure 3-107 individual transmit message buffer assigned to channel b mbccsrn.cha=?0? and mbccsrn.chb=?1? see figure 3-108 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r vfb syb nfb sub seb ceb bvb tcb vfa sya nfa sua sea cea bva tca reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 vfa sya nfa sua sea cea bva tca reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r vfb syb nfb sub seb ceb bvb tcb 0 0 0 0 0 0 0 0 reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? table 3-85. transmit message buffer slot status structure field descriptions field description 15 vfb valid frame on channel b ? protocol related variable: vss!validframe channel b 0 vss!validframe = ?0? 1 vss!validframe = ?1? 14 syb sync frame indicator channel b ? protocol related variable: vrf!header!syfindicator channel b 0 vrf!header!syfindicator = ?0? 1 vrf!header!syfindicator = ?1? 13 nfb null frame indicator channel b ? protocol related variable: vrf!header!nfindicator channel b 0 vrf!header!nfindicator = ?0? 1 vrf!header!nfindicator = ?1? 12 sub startup frame indicator channel b ? protocol related variable: vrf!header!sufindicator channel b 0 vrf!header!sufindicator = ?0? 1 vrf!header!sufindicator = ?1? 11 seb syntax error on channel b ? protocol related variable: vss!syntaxerror channel b 0 vss!syntaxerror = ?0? 1 vss!syntaxerror = ?1? 10 ceb content error on channel b ? protocol related variable: vss!contenterror channel b 0 vss!contenterror = ?0? 1 vss!contenterror = ?1? flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 149 3.4.5.3 message buffer data field description the message buffer data field is used to store the fram e payload data, or a part of it, of the frame to be transmitted to or received from the flexray bus. the minimum required length of this field depends on the message buffer type that the physical mess age buffer is assigned to and is given in table 3-86 . the structure of the message buffer data field is given in figure 3-109 . 9 bvb boundary violation on channel b ? protocol related variable: vss!bviolation channel b 0 vss!bviolation = ?0? 1 vss!bviolation = ?1? 8 tcb transmission conflict on channel b ? protocol related variable: vss!txconflict channel b 0 vss!txconflict = ?0? 1 vss!txconflict = ?1? 7 vfa valid frame on channel a ? protocol related variable: vss!validframe channel a 0 vss!validframe = ?0? 1 vss!validframe = ?1? 6 sya sync frame indicator channel a ? protocol related variable: vrf!header!syfindicator channel a 0 vrf!header!syfindicator = ?0? 1 vrf!header!syfindicator = ?1? 5 nfa null frame indicator channel a ? protocol related variable: vrf!header!nfindicator channel a 0 vrf!header!nfindicator = ?0? 1 vrf!header!nfindicator = ?1? 4 sua startup frame indicator channel a ? protocol related variable: vrf!header!sufindicator channel a 0 vrf!header!sufindicator = ?0? 1 vrf!header!sufindicator = ?1? 3 sea syntax error on channel a ? protocol related variable: vss!syntaxerror channel a 0 vss!syntaxerror = ?0? 1 vss!syntaxerror = ?1? 2 cea content error on channel a ? protocol related variable: vss!contenterror channel a 0 vss!contenterror = ?0? 1 vss!contenterror = ?1? 1 bva boundary violation on channel a ? protocol related variable: vss!bviolation channel a 0 vss!bviolation = ?0? 1 vss!bviolation = ?1? 0 tca transmission conflict on channel a ? protocol related variable: vss!txconflict channel a 0 vss!txconflict = ?0? 1 vss!txconflict = ?1? table 3-86. message buffer data field minimum length physical message buffer assigned to minimum length defined by individual message buffer in segment 1 mbdsr.mbseg1ds receive shadow buffer in segment 1 mbdsr.mbseg1ds individual message buffer in segment 2 mbdsr.mbseg2ds receive shadow buffer in segment 2 mbdsr.mbseg2ds receive fifo for channel a rfdsr.entry_size (rfsr.sel = 0) table 3-85. transmit message buffer slot status structure field descriptions (continued) field description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 150 freescale semiconductor note the flexray module will not access any locations outside the message buffer data field boundaries given by table 3-86 . figure 3-109. message buffer data field structure the message buffer data field is located in the fr m; thus, the flexray module has no means to control application write access to the field. to ensure data consistency, the a pplication must follow a write and read access scheme. 3.4.5.3.1 message buffer data field read access for transmit message buffers, the fl exray module will not mo dify the content of the message buffer data field. thus the application can read back the data at any time wit hout any impact on data consistency. for receive message buffers the application must lock the related re ceive message buffer and retrieve the message buffer header index from the message buffer index registers (mbidxrn) . while the message buffer is locked, the flexray module will not update the message buffer data field. for receive fifos, the application can read the message buffer indicated by the receive fifo a read index register (rfarir) or the receive fifo b read i ndex register (rfbrir) when the related receive fifo non-empty interrupt flag fnea if or fnebif is set in the global interrupt flag and enable register (gifer) . while the non-empty interrupt flag is set, the flexray module will not update the message buffer data field related to message buffer indicated by receive fifo a read index register (rfarir) or the receive fifo b read index register (rfbrir) . 3.4.5.3.2 message buffer data field write access for receive message buffers, receive shadow buffers, a nd receive fifos, the application must not write to the message buffer data field. for transmit message buffers, the application must follow the wr ite access restrictions given in table 3-87 . receive fifo for channel b rfdsr.entry_size (rfsr.sel = 1) 1514131211109876543210 0x0 data0 / mid0 / nmv0 data1 / mid1 / nmv1 0x2 data2 / nmv2 data3 / nmv3 ... ... ... 0xn-2 data n-2 data n-1 table 3-86. message buffer data field minimum length physical message buffer assigned to minimum length defined by flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 151 3.4.6 individual message buff er functional description the flexray module provides three basi c types of individual message buffers: 1. single transmit message buffers 2. double transmit message buffers 3. receive message buffers before an individual message buffer can be used, it must be configured by the appl ication. after the initial configuration, the message buffer can be reconfigured later. the set of the configuration data for individual message buffers is given in section 3.4.3.4.1, ?individual message buffer configuration data ?. 3.4.6.1 individual message buffer configuration the individual message buffer configur ation consists of two steps. the fi rst step is the allocation of the required amount of memory for the frm. the sec ond step is the programming of the message buffer configuration registers, which is described in this section. 3.4.6.1.1 common configuration data one part of the message buffer c onfiguration data is common to all individual message buffers and the receive shadow buffers. these data can onl y be set when the protocol is in the poc:config state. the application configures the num ber of utilized individual messag e buffers by writing the message buffer number of the last utilized message buffer into the last_mb_util field in the message buffer segment size and utilizat ion register (mbssutr) . table 3-87. frame data write access constraints field single buffered double buffered commit side transmit side data, mid, nmv poc:config or mb_dis or mb_lck poc:config or mb_dis or mb_lck poc:config or mb_dis table 3-88. frame data field descriptions field description data[0:n-1] message data ? provides the message data received or to be transmitted. for receive message buffer and receive fifos, this field provides the message data received for this message buffer. for transmit message buffers, the field provides the message data to be transmitted. mid[0:1] message identifier ? if the payload preamble bit ppi is set in the message buffer frame header, the mid field holds the message id of a dynamic frame located in the message buffer. the re ceive fifo filter uses the received message id for message id filtering. nmv[0:11] network management vector ? if the payload preamble bit ppi is set in the message buffer frame header, the network management vector field holds the network managem ent vector of a static frame located in the message buffer. note: the mid and nmv bytes replace the corresponding data bytes. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 152 freescale semiconductor the application configures the si ze of the two segments of individual message buffers by writing the message buffer number of the last me ssage buffer in the first segment into the last_mb_seg1 field in the message buffer segment size and utilization register (mbssutr) the application configures the length of the message buffer data fields for both of the message buffer segments by writing to the mbseg2 ds and mbseg1ds fields in the message buffer data size register (mbdsr) . depending on the current receive func tionality of the flexray module, th e application must configure the receive shadow buffers. for each segment and for each channel with at le ast one individual receive message buffer assigned, the appli cation must configure the related receive shadow buffer using the receive shadow buffer index register (rsbir) . 3.4.6.1.2 specific configuration data the second part of the message buffer configur ation data is specific for each message buffer. these data can be cha nged only when either ? the protocol is in the poc:config state or ? the message buffer is disa bled, i.e. mbccsrn.eds = 0 the individual message buffer type is defined by the mtd and mbt bits in the message buffer configuration, control, st atus registers (mbccsrn) as given in table 3-89 . the message buffer specific configuration data are 1. mcm, mbt, mtd bits in message buffer configuration, c ontrol, status registers (mbccsrn) 2. all fields and bits in message buffer cycle counter filter registers (mbccfrn) 3. all fields and bits in message buffer frame id registers (mbfidrn) 4. all fields and bits in message buffer inde x registers (mbidxrn) the meaning of the specific configurat ion data depends on the message buffe r type, as given in the detailed message buffer type descriptions section 3.4.6.2, ?single tran smit message buffers ?, section 3.4.6.3, ?receive message buffers ?, and section 3.4.6.4, ?double transmit message buffer ?. 3.4.6.2 single transmit message buffers the section provides a detail ed description of the func tionality of single buffered transmit message buffers. a single transmit message buffer is used by the application to provide message data to the flexray module that will be transmitted over the fl exray bus. the flexray module uses the transmit message buffers to table 3-89. individual message buffer types mbccsrn.mtd mbccsrn.mbt individual message buffer description 0 0 receive message buffer 01 reserved 1 0 single transmit message buffer 1 1 double transmit message buffer flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 153 provide information about the transm ission process and status informati on about the slot in which message was transmitted. the individual message buffer with message buffer number n is configured to be a single transmit message buffer by the following settings: ? mbccsrn.mbt = ?0? (single buffered message buffer) ? mbccsrn.mtd = ?1? (transmit message buffer) 3.4.6.2.1 access regions to certain message buffer fields, bot h the application and the flexray m odule have access. to ensure data consistency, a message buffer locking scheme is implem ented, which is used to control the access to the data, control, and status bits of a message buffer. the access regions for single transmit message buffers are depicted in figure 3-110 . a description of the regions is given in table 3-90 . if an region is active as indicated in table 3-91 , the access scheme given for that region applies to the message buffer. figure 3-110. single transmit message buffer access regions the trigger bits mbccsrn.edt and mbccsrn.lckt, and the interrupt enable bit mbccsrn.mbie are not under access control and can be accessed from the application at any time. the status bits table 3-90. single transmit message buffer access regions description region access from region used for application module cfg read/write - message buffer configuration msg read/write - message data and slot status access nf - read-only message header access for null frame transmission tx - read/write message transmission and slot status update cm - read-only message buffer validation sr - read-only message buffer search message buffer data field: data[0-n] message buffer header field: frame header mbccsrn.cmt message buffer header field: slot status message buffer header field: data field offset mbccfrn.mtm/cha/chb/ccf* mbfidrn.fid mbidxrn.mbidx mbccsrn.mbt/mtd tx nf cmt sr cfg msg flexray module (flexrayv2) mfr4300 data sheet, rev. 3 154 freescale semiconductor mbccsrn.eds and mbccsrn.lcks are not under access control and can be accessed from the flexray module at any time. the interrupt flag mbccsnr.mbif is not under access control and ca n be accessed from the application and the flexray module at any time. flex ray module clear access has higher priority. the flexray module restricts its acces s to the regions depending on the cu rrent state of the message buffer. the application must adhere to these restrictions in order to ensure data consistency. the transmit message buffer states are given in figure 3-111 . a description of the states is given in table 3-91 , which also provides the access scheme for the access regions. the status bits mbccsrn.eds a nd mbccsrn.lcks provide the applic ation with the required message buffer status information. the internal status information is not visible to the application. 3.4.6.2.2 message buffer states this section describes the transmit message buffer states and provides a state diagram. figure 3-111. single transmit message buffer states table 3-91. single transmit message buffer state description (sheet 1 of 2) state mbccsrn access region description eds lcks appl. module idle 1 0 ? cm, sr id l e - message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. hdislck 0 1 cfg ? dis abled and l ock ed - message buffer under configuration. excluded from message buffer search. hlck 1 1 msg sr l ock ed - applications access to data, control, and status. included in message buffer search. hlckccsa hl hlck hdislck hdis idle cctx he hlckccma sa ccsa ccma sa ma tx reset_state dss dss ccnf sss sts hlckccnf sts sss sts hu hd hl hu hl hu hl hu hl hu he hd sts ccsu su sss dss dss ma flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 155 3.4.6.2.3 message buffer transitions application transitions the application transitions can be triggered by th e application using the commands described in table 3-92 . the application issues the commands by writing to the message buffer configuration, control, status registers (mbccsrn) . only one command can be issu ed with one write access. each command is executed immediately. if the command is ignored, it must be issued again. the enable and disable commands issued by writing ?1? to the trig ger bit mbccsrn.edt. the transition that will be triggered by each of these comma nd depends on the current va lue of the status bit mbccsrn.eds. if the command tri ggers the disable transition hd and the message buffer is in one of the states ccsa , hlckccsa , ccma , hlckccma, ccnf , hlckccnf , or cctx , the disable transition has no effect (command is ignored) and the message buf fer state is not changed. no notification is given to the application. the lock and unlock commands issu ed by writing ?1? to the trigger bit mbccsrn.lckt. the transition that will be triggered by each of these commands depends on the current value of the status bit mbccsrn.lcks. if the command triggers the lock transition hl and the message buffer is in the state cctx, the lock transition has no effect (command is ignored) and messa ge buffer state is not changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (chierfr) is set. ccsa 10?? s lot a ssigned - message buffer assigned to next static slot. ready for null frame transmission. hlckccsa 1 1 msg ? l ock ed and s lot a ssigned - applications access to data, control, and status.message buffer assigned to next static slot ccnf 1 0 ? nf n ull f rame transmission header is used for null frame transmission. hlckccnf 1 1 msg nf l ock ed and n ull f rame transmission - applications access to data, control, and status. header is used for null frame transmission. ccma 1 0 ? cm m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. hlckccma 1 1 msg ? l ock ed and m essage a vailable - applications access to data, control, and status. message buffer is assigned to next slot and cycle counter filter matches. cctx 10?tx message t ransmission - message buffer data transmit. payload data from buffer transmitted ccsu 1 0 ? tx s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. table 3-92. single transmit message buffer application transitions transition command condition description he mbccsrn.edt:= 1 mbccsrn.eds = 0 application triggers message buffer enable. hd mbccsrn.eds = 1 application triggers message buffer disable. table 3-91. single transmit message buffer state description (sheet 2 of 2) state mbccsrn access region description eds lcks appl. module flexray module (flexrayv2) mfr4300 data sheet, rev. 3 156 freescale semiconductor module transitions the module transitions that can be trigge red by the flexray module are described in table 3-93 . each transition will be triggered for certain message buffers when the related condition is fulfilled. transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 3-94 , the module transitions have a highe r priority than the application transitions. for all states except the ccma state, both a lock/unlock transition hl/hd and a module transition can be executed at the same time. the resu lt state is reached by first applying the application transition and subsequently the module transition to the intermediately reached state. for example, if the message buffer is in the hlck state and the application unl ocks the message buffer by the hu transition and the module triggers th e slot assigned transition sa , the intermediate state is idle and the resulting state is ccsa . the priorities among the module transiti ons is given in the second part of table 3-94 . hl mbccsrn.lckt:= 1 mbccsrn.lcks = 0 application triggers message buffer lock. hu mbccsrn.lcks = 1 application triggers message buffer unlock. table 3-93. single transmit message buffer module transitions transition condition description sa slot match and static slot s lot a ssigned - message buffer is assigned to next static slot. ma slot match and cyclecounter match m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. tx slot start and mbccsrn.cmt = ?1? t ransmission slot start - slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. su status updated s tatus u pdated - slot status field and messa ge buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart - start of static slot. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart. - start of dynamic slot or symbol window or nit. sss slot start or symbol window start or nit start s lot or s egment s tart - start of static slot or dy namic slot or symbol window or nit. table 3-94. single transmit message buffer transition priorities state priorities description module vs. application idle, hlck sa > hd ma > hd slot assigned > message buffer disable message available > message buffer disable ccma tx > hl transmission start > message buffer lock table 3-92. single transmit message buffer application transitions transition command condition description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 157 3.4.6.2.4 transmit message setup to transmit a message over the flex ray bus, the application writes the message data into the message buffer data field and sets the commit bit cmt in the message buffer configuration, control, status registers (mbccsrn) . the physical access to the message bu ffer data field is described in section 3.4.3.1, ?individual message buffers ?. as indicated by table 3-91 , the application shall write to the me ssage buffer data field and change the commit bit cmt only if the transmit messa ge buffer is in one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma. a message buffer can be identi fied for message transmission only if it is the idle state. the application can change the st ate of a message buffe r if it issues the appropriate commands given in table 3-92 . the state change is indicat ed through the mbccsrn.eds and mbccsrn.lcks status bits. if the transmit message buffe r enters one of the states hdis, hdislck, hlck, hlckccsa, hlckccma, or hlckccma the mbccsrn.dval flag is negated. 3.4.6.2.5 message transmission as a result of the message buffer search described in section 3.4.7, ?individual message buffer search ?, the flexray module triggers th e message available transition ma for up to two transmit message buffers. this changes the message buffer state from idle to ccma and the message buffers can be used for message transmission in the next slot. the flexray module transmits a message from a messa ge buffer if both of the following two conditions are fulfilled at the start of the transmission slot: 1. the message buffer is in the message available state ccma 2. the message data are still valid, i.e. mbccsrn.cmt = ?1? in this case, the flexra y module triggers the tx transition and changes th e message buffer state to cctx . a transmit message buffer timing and state change diagram for message tr ansmission is given in figure 3-112 . in this example, the message buf fer with message buffer number n is idle at the start of the search slot, matches the slot and cycle number of th e next slot, and message buffer data are valid, i.e. mbccsrn.cmt = ?1?. module internal idle, hlck ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start table 3-94. single transmit message buffer transition priorities state priorities description flexray module (flexrayv2) mfr4300 data sheet, rev. 3 158 freescale semiconductor figure 3-112. message transmission timing figure 3-113. message transmission from hlck state with unlock the amount of message data read fr om the frm and transferred to the flexray bus is determined by the following three items 1. the message buffer segment that the messag e buffer is assigned to, as defined by the message buffer segment size and util ization register (mbssutr) . 2. the message buffer data field size, as defined by the related field of the message buffer data size register (mbdsr) 3. the value of the pldlen field in the messa ge buffer header fi eld, as described in section 3.4.5.2.1, ?frame header section description ? if a message buffer is assigned to message buf fer segment 1, and pldlen > mbseg1ds, then 2 * mbseg1ds bytes will be read from the message buffer data field and zero padding is used for the remaining bytes for the flexray bus transfer. if pldlen <= mbseg1 ds, the flexray module reads and transfers 2*pldlen bytes. the same holds for segment 2 and mbseg2ds. 3.4.6.2.6 null fr ame transmission a static slot with slot number s is assigned to the flexray module for ch annel a, if at least one transmit message buffer is configured with the mbfidrn.fid set to s and mbccfrn.cha set to ?1?. a null frame is transmitted in the static slot s on channel a, if this slot is assigned to the flexray module for channel a, and all transmit message buffers with mbfidrn.fid = s a nd mbccfrn.cha = ?1? are either not committed, i.e mbccsrn.cmt = ?0?, or locked by the application, i.e. mbccsrn.lcks = ?1?, or the cycle counter filter is enabled and does not match. additionally, the application can clear the commit b it of a message buffer that is in the ccma state, which is called uncommit or transmit abort . this message buffer will be used for null frame transmission. as a result of the message buffer search described in section 3.4.7, ?individual message buffer search ?, the flexray module triggers the slot assigned transition sa for up to two transmit message buffers if at search[s+1] mt start ma slot s tx su ccma cctx slot s+1 idle mt start idle slot s+2 slot start slot start slot start mt start message transmit sss ccsu search[s+1] mt st a rt m t s ta r t ma slot s tx sss hlckccma cctx slot s+1 hlck m t st a r t idle slot s+2 slot start slot start slot start hu ccma message transmit flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 159 least one of the conditions menti oned above is fulfilled for thes e message buffers. the transition sa changes the message buffer states from either idle to ccsa or from hlck to hlckccsa . in each case, these message buffers will be used for null frame tr ansmission in the next slot. a message buffer timing and state change diagram for null frame transmission from idle state is given in figure 3-114 . figure 3-114. null frame transmission from idle state a message buffer timing and st ate change diagram for nul l frame transmission from hlck state is given in figure 3-115 . figure 3-115. null frame transmission from hlck state if a transmit message buffer is in the ccsa or hlckccsa state at the start of th e transmission slot, a null frame is transmitted in any case, even if the me ssage buffer is unlocked or committed before the transmission slot starts. a tran smit message buffer timing and stat e change diagra m for null frame transmission for this case is given in figure 3-116 . figure 3-116. null frame transmission from hlck state with unlock since the null frame transmission will not use the messa ge buffer data, the appli cation can lock/unlock the message buffer during null frame tr ansmission. a transmit message buffer timing and state change diagram for null frame transmissi on for this case is given in figure 3-117 . search[s+1] m t s t ar t mt start sa slot s sts sss ccsa ccnf slot s+1 idle m t s ta r t idle slot s+2 slot start slot start slot start null frame transmit search[s+1] m t s t art m t s t art sa slot s sts sss hlckccsa hlckccnf slot s+1 hlck m t s t art hlck slot s+2 slot start slot start slot start null frame transmit search[s+1] m t star t mt s t art sa slot s sts sss hlckccsa ccnf slot s+1 hlck mt start idle slot s+2 slot start slot start slot start hu ccsa null frame transmit flexray module (flexrayv2) mfr4300 data sheet, rev. 3 160 freescale semiconductor figure 3-117. null frame transmission from with locking 3.4.6.2.7 message buffer status update after the end of each slot, the pe generates the sl ot status vector. depending on the this status, the transmitted frame type, and the amount of transmitted data, the message buffer status is updated. message buffer status update a fter complete message transmission the term complete message transmissi on refers to the fact that all payload data stored in the message buffer were send to flexray bus. in this case, the flexray module updates the sl ot status field of the message buffer and triggers the status updated transition su . with the su transition, the flexray module sets the message buffer interrupt flag mbccsn.mbi f to indicate the successf ul message transmission. depending on the transmission mode flag mbccf rn.mtm, the flexray module changes the commit flag mbccsrn.cmt and the valid flag mbccsrn.dv al. if the mbccfrn.mtm flag is negated, the message buffer is in the event transmission mode. in this case, each committed message is transmitted only once. the commit flag mbccsr n.cmt is cleared with the su transition. if the mb ccfrn.mtm flag is asserted, the message buffer is in the state transmission mode . in this case, each committed message is transmitted as long as the applicat ion provides new data or locks the message buffers. the flexray module will not clear the mbccsrn.cmt flag at the e nd of transmission and will set the valid flag mbccsrn.dval to indicate that the message will be transmitted again. message buffer status update a fter incomplete message transmission the term incomplete message transmission refers to the fact that not all payload data that should be transmitted were send to flexray bus. this may be caused by the following regular conditions in the dynamic segment: 1. the transmission slot starts in a minisl ot with a minislot number greater than platesttx . 2. the transmission slot did not ex ist in the dynamic segment at all. additionally, an incomplete message transmission can be caused by internal communication errors. if those error occur, the protocol engine communicati on failure interrupt flag pecf_if is set in the protocol interrupt flag register 1 (pifr1) . in any of these two cases, the status of the message buffer is not ch anged at all with th e su transition. the slot status field is not updated, the status and contro l flags are not changed, and th e interrupt flag is not set. search[s+1] mt start m t s t ar t sa slot s st ss slot s+1 idle m t s ta r t hlck slot s+2 slot start slot start slot start null frame transmit hl ccsa ccnf hlckccnf flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 161 message buffer status update after null frame transmission after the transmission of a null fram e, the status of the message buffe r that was used for the null frame transmission is not changed at all. the slot status field is not updated, the status and control flags are not changed, and the interrupt flag is not set. 3.4.6.3 receive message buffers the section provides a detailed description of th e functionality of the receive message buffers. a receive message buffer is used to receive a message from the flex ray bus based on individual filter criteria. the flexray module uses the receive mess age buffer to provide the following data to the application 1. message data received 2. information about the reception process 3. status information about the slot in which the message was received a individual message buffer with message buffer number n is configured as a receive message buffer by the following configuration settings ? mbccsrn.mbt = ?0? (single buffered message buffer) ? mbccsrn.mtd = ?0? (receive message buffer) to certain message buffer fields, bot h the application and the flexray m odule have access. to ensure data consistency, a message buffer locking scheme is implem ented that is used to c ontrol the access to the data, control, and status bits of a messa ge buffer. the access regions for rece ive message buffers are depicted in figure 3-118 . a description of the regions is given in table 3-95 . if an region is active as indicated in table 3-96 , the access scheme given for that region applies to the message buffer. figure 3-118. receive message buffer access regions message buffer data field: data[0-n] message buffer header field: frame header mbccsrn.dval/dup message buffer header field: slot status message buffer header field: data field offset mbccfrn.cha/chb/ccf* mbfidrn.fid mbidxrn.mbidx mbccsrn.mtd rx sr cfg msg flexray module (flexrayv2) mfr4300 data sheet, rev. 3 162 freescale semiconductor the trigger bits mbccsrn.edt a nd mbccsrn.lckt and the interrupt enable bit mbccsrn.mbie are not under access control and can be accessed from th e application at any time. the status bits mbccsrn.eds and mbccsrn.lcks are not under access control and can be accessed from the flexray module at any time. the interrupt flag mbccsr n.mbif is not under access control a nd can be accessed fro m the application and the flexray module at any time. flex ray module set access has higher priority. the flexray module restricts its acces s to the regions depending on the cu rrent state of the message buffer. the application must adhere to these restrictions in order to ensure da ta consistency. the receive message buffer states are given in figure 3-119 . a description of the messag e buffer states is given in table 3-91 , which also provides the access scheme for the access regions. the status bits mbccsrn.eds and mbccsrn.lcks pr ovide the application wi th the required status information. the internal status informat ion is not visible to the application. figure 3-119. receive message buffer states table 3-95. receive message buffer access region description region access from region used for application module cfg read/write - message buffer configuration, message data and status access msg read/write - message data, header, and status access rx - write-only message reception and status update sr - read-only message buffer search data table 3-96. receive message buffer states and access (sheet 1 of 2) state mbccsrn access from description eds lcks appl. module idle 10?sr id l e - message buffer is idle. included in message buffer search. hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. reset_state hlck hdislck hdis idle hlckccbs su ccbs bs sls sns sns hl hu he hd hl he hd hu hl hu ccsu bs ccrx hl hu hlckccrx sls sss sss flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 163 3.4.6.3.1 message buffer transitions application transitions the application transitions that ca n be triggered by the application using the commands described in table 3-97 . the application issues the commands by writing to the message buffer configuration, control, status registers (mbccsrn) . only one command can be issu ed with one write access. each command is executed immediately. if the command is ignored, it must be issued again. the enable and disable commands issued by writing ?1? to the trig ger bit mbccsrn.edt. the transition that will be triggered by each of these comma nd depends on the current va lue of the status bit mbccsrn.eds. if the command tri ggers the disable transition hd and the message buffer is in one of the states ccbs , hlckccbs , or ccrx , the disable transition has no effe ct (command is ignored) and the message buffer state is not changed. no not ification is given to the application. the lock and unlock commands issu ed by writing ?1? to the trigger bit mbccsrn.lckt. the transition that will be triggered by each of these commands depends on the current value of the status bit mbccsrn.lcks. if the command triggers the lock transition hl while the message buffer is in the state ccrx, the lock transition has no effect (command is ignored) and messag e buffer state is not changed. in this case, the message buffer lock error flag lck_ef in the chi error flag register (chierfr) is set. hdislck 0 1 cfg ? dis abled and l ock ed - message buffer under configuration. excluded from message buffer search. hlck 1 1 msg ? l ock ed - applications access to data, control, and status. included in message buffer search. ccbs 10?? b uffer s ubscribed - message buffer subscribed for reception. filter matches next (slot, cycle, channel) tuple. hlckccbs 1 1 msg ? l ock ed and b uffer s ubscribed - applications access to data, control, and status. message buff er subscribed for reception. ccrx 10?? message r eceive - message data received into related shadow buffer. hlckccrx 1 1 msg ? l ock ed and message r eceive - applications access to data, control, and status. message data received into related shadow buffer. ccsu 1 0 ? rx s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. table 3-97. receive message buffer application transitions transition host command condition description he mbccsrn.edt:= 1 mbccsrn.eds = 0 application triggers message buffer enable. hd mbccsrn.eds = 1 application triggers message buffer disable. hl mbccsrn.lckt:= 1 mbccsrn.lcks = 0 application triggers message buffer lock. hu mbccsrn.lcks = 1 application triggers message buffer unlock. table 3-96. receive message buffer states and access (sheet 2 of 2) state mbccsrn access from description eds lcks appl. module flexray module (flexrayv2) mfr4300 data sheet, rev. 3 164 freescale semiconductor module transitions the module transitions that can be trigge red by the flexray module are described in table 3-98 . each transition will be triggered for certain message buffers when the related condition is fulfilled. transition priorities the application can tr igger only one transition at a time. there is no need to sp ecify priorities among them. as shown in table 3-99 , the module transitions have a higher priority than the application transitions. for all states except the ccrx state, a module trans ition and the application lock/unlock transition hl/hu and can be executed at the same time. the result stat e is reached by first applyi ng the module transition and subsequently the application transitio n to the intermediately reached state. for example, if the message buffer is in the buffer subscribed state ccbs and the module triggers the slot start transition sls at the same time as the application locks the message buffer by the hl transition, the inte rmediate state is ccrx and the resulting state is locked buffer subscribed state hlckccrx . 3.4.6.3.2 message buffer search the flexray module starts a sequential search that checks all message buffers at the following protocol related events: ? slot start, in the static frame segment ? minislot start, in the dynamic frame segment ?nit start the filters that are used for the search are described in section 3.4.7.1, ?individual message buffer filtering ?. table 3-98. receive message buffer module transitions transition condition description bs slot match and cyclecounter match b uffer s ubscribed - the message buffer filter matches next slot and cycle. sls slot start sl ot s tart - start of either static slot or dynamic slot. sns symbol window start or nit start s ymbol window or n it s tart - start of either symbol window or nit. sss slot start or symbol window start or nit start sl ot or s egment s tart - start of either static slot, dynamic slot, symbol window, or nit. su status updated s tatus u pdated - slot status field, message bu ffer status flags, header index updated. interrupt flag set. table 3-99. receive message buffer transition priorities state priorities description module vs. application idle bs > hd buffer subscribed > message buffer disable hlck bs > hd buffer subscribed > message buffer disable ccrx sss > hl slot or segment start > message buffer lock flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 165 as a result of the message buffer se arch, the flexray module changes the state of up to two enabled receive message buffers from either idle state idle or locked state hlck to the either subscribed state ccbs or locked buffer subscribed state hlckccbs by triggering the buffer subscribed transition bs. if the receive message buffers for the next slot are assigned to both channels, then at most one receive message buffer is changed to a buffer subscribed state . if more than one matching message buffers assigned to a certain channe l, then only the message buffer with the lowest message buffer number is in one of the states mentioned above. 3.4.6.3.3 message reception with the start of the next static or dynamic sl ot the module trigger th e slot start transition sls . this changes the state of the subscribed receive message buffe rs from either ccbs to ccrx or from hlckccbs to hlckccrx, respectively. during the reception slot, the recei ved frame data are written into the shadow buffers. for details on receive shadow buffers, see section 3.4.6.3.6, ?receive shadow buffers concept ?. the data and status of the receive message buffers that are the ccrx or hlckccrx are not modified in the reception slot. 3.4.6.3.4 message buffer status update with the start of the next static or dynamic slot or with th e start of the symbol wi ndow or nit, the module trigger the slot or segment start transition sss . this transition changes the state of the receiving receive message buffers from either ccrx to ccsu or from hlckccrx to hlck, respectively. if a message buffer was in the locked state hlckccrx , no update will be perfor med. the received data are lost. this is indica ted by setting the frame lost channel a/ b error flag frla_e f/frlb_ef in the chi error flag register (chierfr) . if a message buffer was in the ccrx state it is now in the ccsu state. after the evaluation of the slot status provided by the pe the message buffer is upd ated. the message buffer update depends on the slot status bits and the segment the message buff er is assigned to. this is described in table 3-100 . table 3-100. receive message buffer update vss!validframe vrf!header!nfindicator update description 11 valid non-null frame received. - message buffer data field updated. - frame header field updated. - slot status field updated. - dup:= 1 - dval:= 1 - mbif:= 1 10 valid null frame received. - message buffer data field not updated. - frame header field not updated. - slot status field updated. - dup:= 0 - dval not changed - mbif:= 1 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 166 freescale semiconductor note if the number of the last slot in th e current communication cycle on a given channel is n , then all receive message buffers assigned to this channel with mbfidrn.fid > n will not be updated at all. when the receive message buffer update ha s finished the status updated transition su is triggered, which changes the buffer state from ccsu to idle . an example receive message buffer timing and state change diagram for a normal fram e reception is given in figure 3-120 . figure 3-120. message reception timing the amount of message data written into the message buffer data field of the receive shadow buffer is determined by the following two items: 1. the message buffer segment that the messag e buffer is assigned to, as defined by the message buffer segment size and util ization register (mbssutr) . 2. the message buffer data field size, as defined by the related field of the message buffer data size register (mbdsr) 3. the number of bytes received over the flexray bus if the message buffer is assigned to the message buffe r segment 1, and the number of received bytes is greater than 2*mbdsr.mbseg1ds, the flexra y module writes only 2*m bdsr.mbseg1ds bytes into the message buffer data field of the receive shadow buffer. if the num ber of received bytes is less than 2*mbdsr.mbseg1ds, the fl exray module writes only the receive d number of bytes and will not change the trailing bytes in the message buffer data fi eld of the receive shadow buffer. the same holds for the message buffer segment 2 with mbdsr.mbseg2ds. 0x no valid frame received. - message buffer data field not updated. - frame header field not updated. - slot status field updated. - dup:= 0 - dval not changed. - mbif:= 1, if the slot was not an empty dynamic slot. note: an empty dynamic slot is indicated by the following frame and slot status bit values: vss!validframe = 0 and vss!syntaxerror = 0 and vss!contenterror = 0 and vss!bviolation = 0. table 3-100. receive message buffer update (continued) vss!validframe vrf!header!nfindicator update description search[s+1] mt st a rt bs slot s sls su ccbs ccrx slot s+1 idle mt start idle slot s+2 slot start slot start mt st a rt message receive to receive shadow buffer sss ccsu slot start flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 167 3.4.6.3.5 received message access to access the message data received over the flexray bus, the application reads the message data stored in the message buffer data field of the corresponding receive message buffer. the access to the message buffer data field is described in section 3.4.3.1, ?individual message buffers ?. the application can read the message buffer data field if the receive me ssage buffer is one of the states hdis, hdislck, or hlck. if the message buffer is in one of th ese states, the flexray module will not change the content of the message buffer. 3.4.6.3.6 receive shadow buffers concept the receive shadow buffer concept applies only to individua l receive message buffers. the intention of this concept is to ensure that only syntactically and se mantically valid received non-null frames are presented to the application in a receive message buffer. the basic structure of a receive shadow buffer is described in section 3.4.3.2, ?receive shadow buffers ?. the receive shadow buffers temporar ily store the received frame header and message data. after the slot boundary the slot status information is generated. if the slot status info rmation indicates the reception of the valid non-null frame (see table 3-100 ), the flexray module writes the slot status into the slot status field of the receive shadow buffer and exchanges the content of the message buffer index registers (mbidxrn) with the content of the corresponding internal sh adow buffer index register. in all other cases, the flexray module writes the slot st atus into the identified receive message buffer, depending on the slot status and the flexray segment the message buffer is assigned to. the shadow buffer concept, with its index exchange, results in the fact that the frm located message buffer associated to an individual receive message buffer ch anges after successful reception of a valid frame. this means that the message buffer area in the frm accessed by the application for reading the received message is different from the initial setting of the message buffer. therefore, the application must not rely on the index informati on written initially into the message buffer inde x registers (mbidxrn) . instead, the index of the message buffer h eader field must be fetched from the message buffer index registers (mbidxrn) . 3.4.6.4 double transmit message buffer the section provides a detailed description of the functionality of the double transmit message buffers. double transmit message buffers are used by the app lication to provide the flexray module with the message data to be transmitted over the flexray bu s. the flexray module uses this message buffer to provide information to the a pplication about the transmi ssion process, and status information about the slot in which message data was transmitted. in contrast to the single transmit message buffers, the application can provide new transmis sion data while the transmission of the previously provided message data is running. this scheme is called double buffering and can be considered as a fifo of depth 2. double transmit message buffers are implemented by combining two indi vidual message buff ers that form the two sides of an double transmit me ssage buffer. one side is called the commit side and will be accessed by the application to provi de the message data. the other side is called the transmit side and is used by the flexray module (flexrayv2) mfr4300 data sheet, rev. 3 168 freescale semiconductor flexray module to transmit the message data to the flexray bus. the two sides are located in adjacent individual message buffers. the messa ge buffer that implements the commit side has an even message buffer number 2n. the transmit side message buffer fo llows the commit side message buffer and has the message buffer number 2n+1. the basic structure and data flow of a double tr ansmit message buffer is given in figure 3-121 . figure 3-121. double transmit buffer structure and data flow note both the commit and the transmit side must be configured with identical values except for the message buffer index registers (mbidxrn) . 3.4.6.4.1 access regions to certain message buffer fields, bot h the application and the flexray m odule have access. to ensure data consistency, a message buffer locki ng scheme is implemented, which cont rols the exclusive access to the data, control, and status bits of the message buffer. the access scheme for double transmit message buffers is depicted in figure 3-122 . the given regions represent fields that can be accessed from both the application and the flexray module and, thus, require access restrictions. a descripti on of the regions is given in table 3-101 . figure 3-122. double transmit message buffer access regions layout commit side transmit side application flexray bus mb# 2n mb# 2n+1 internal message transfer message data message data message data message buffer data field: data[0-n] message buffer header field: frame header mbccsr[2n]n.cmt message buffer header field: slot status message buffer header field: data field offset mbccfr[2n].mtm/cha/chb/ccf* mbfidr[2n].fid mbidxr[2n].mbidx mbccsr[2n].mbt/mtd message buffer data field: data[0-n] message buffer header field: frame header mbccsr[2n+1].cmt message buffer header field: slot status message buffer header field: data field offset mbccfr[2n+1].mtm/cha/chb/ccf* mbfidr[2n+1].fid mbidxr[2n+1].mbidx mbccsr[2n+1].mbt/mtd commit side transmit side cfg msg cfg itx ss ss sr tx flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 169 the trigger bits mbccsrn.edt and mbccsrn.lckt, and the interrupt enable bit mbccsrn.mbie are not under access control and can be accessed from the application at any time. the status bits mbccsrn.eds and mbccsrn.lcks are not under access control and can be accessed from the flexray module at any time. the interrupt flag mbccsnr.mbif is not under access control and ca n be accessed from the application and the flexray module at any time. flex ray module set access has higher priority. the flexray module restricts its access to the regi ons, depending on the current state of the corresponding part of the double transmit message buf fer. the application must adhere to these restrictions in order to ensure data consistency. the states for the commit side of a double tr ansmit message buffer are given in figure 3-123 . a description of the states is given in table 3-103 . the states for the tr ansmit side of a double transmit message buffer are given in figure 3-124 . a description of the states is given in table 3-103 . the description tables also provide th e access scheme for the access regions. the status bits mbccsrn.eds a nd mbccsrn.lcks provide the applic ation with the required message buffer status information. the internal status information is not visible to the application. 3.4.6.4.2 message buffer states this section describes the transmit message buffer states and provides a state diagram. table 3-101. double transmit message buffer access regions description access description region type application module commit side cfg read/write - message buffer configuration msg read/write - message buffer data and control access itx - read/write internal message transfer. ss - write-only slot status update transmit side cfg read/write - message buffer configuration sr - read-only message buffer search tx - read-only internal message transfer, message transmission ss - write-only slot status update flexray module (flexrayv2) mfr4300 data sheet, rev. 3 170 freescale semiconductor figure 3-123. double transmit message buffer state diagram (commit side) a description of the states of the commit side of a double tran smit message buffer is given in table 3-102 . table 3-102. double transmit message buffer state description (commit side) state mbccsr[2n] access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled - message buffer under configuration. commit side can not be used for internal message transfer. ccitx 1 0 ? itx i nternal message t ransfer - message buffer data transferred from commit side to transmit side. commit side specific states idle 1 0 ? itx, ss idle - message buffer commit side is idle. commit side can be used for internal message transfer. hdislck 0 1 cfg ss dis abled and l ock ed - message buffer under configuration. commit side can not be used for internal message transfer. hlck 1 1 msg ss l ock ed - applications access to data, control, and status. commit side can not be used for internal message transfer. hlck hdislck hdis idle ccitx is ie reset_state he hd hl hu he hd hl hu flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 171 figure 3-124. double transmit message buffer state diagram (transmit side) a description of the states of the transmit side of a double transmit message buffer is given in table 3-103 . table 3-103. double transmit message buffer state description (transmit side) (sheet 1 of 2) state mbccsrn access region description eds lcks appl. module common states hdis 0 0 cfg ? dis abled - message buffer under configuration. excluded from message buffer search. ccitx 1 0 ? tx i nternal m essage t ransfer - message buffer data transferred from commit side to transmit side. transmit side specific states idle 1 0 ? sr idle - message buffer transmit side is idle. transmit side is included in message buffer search. ccsa 1 0 ? ? s lot a ssigned - message buffer assigned to next static slot. ready for null frame transmission. ccsaccitx 1 0 ? tx s lot a ssigned and i nternal m essage t ransfer - message buffer assigned to next static slot and message buffer data transferred from commit side to transmit side. ccnf 1 0 ? tx n ull f rame transmission header is used for null frame transmission. ccnfccitx 1 0 ? tx n ull f rame transmission and i nternal m essage t ransfer - header is used for null frame transmission and message buffer data transferred from commit side to transmit side. ccma 1 0 ? ? m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. ccmaccitx 1 0 ? ? m essage a vailable and i nternal m essage t ransfer - message buffer is assigned to next slot and cycle counter filter matches and message buffer data transferred from commit side to transmit side. cctx 1 0 ? tx message t ransmission - message buffer data transmit. payload data from buffer transmitted ccsaccitx ccitx hdis idle cctx ccmaccitx ccsa ccma sa ma tx reset_state dss ccnf sss sts ccnfccitx is ie is ie is ie he hd sts ccsu su sss dss is ie flexray module (flexrayv2) mfr4300 data sheet, rev. 3 172 freescale semiconductor 3.4.6.4.3 message buffer transitions application transitions the application transitions that ca n be triggered by the application using the commands described in table 3-104 . the application issues the commands by writing to the message buffer configuration, control, status registers (mbccsrn) . only one command can be issu ed with one write access. each command is executed immediately. if the command is ignored, it must be issued again. the enable and disable commands can be issued on the transmit side only. any en able or disable command issued on the commit side will be ignored without not ification. the tr ansitions that will be triggered depends on the value of the eds bit. the enable and disable commands will affe ct both the commit side and the transmit side at the same time. if the application triggers the disable transition hd while the transmit side is in one of the states ccsa , ccsaccitx , ccnf , ccnfccitx , ccma , ccmaccitx, cctx, or ccsu, the disable transition has no effect (command is ignored) and the message buffer state is not changed. no notification is given to the application. the lock and unlock commands can be issued on th e commit side only. any lock or unlock command issued on the transmit side will be ignored and th e double transmit buffer lock error flag dbl_ef in the chi error flag register (chierfr) will be set. the transitions that will be triggered depends on the current value of the lcks bit. th e lock and unlock commands will onl y affect the commit side. if the application triggers the lock transition hl while the commit side is in the state ccitx, the message buffer state will not be changed and the message buffer lock error flag lck_ef in the chi error flag register (chierfr) will be set. module transitions the module transitions that can be trigge red by the flexray module are described in table 3-105 . the transitions c1 and c2 apply to both sides of the message buffer and are applied at the same time. all other flexray module transitions appl y to the transmit side only. ccsu 1 0 ? ss s tatus u pdate - message buffer status update. update of status flags, the slot status field, and the header index. note: the slot status field of the comm it side is updated too, even if the application has locked the commit side. table 3-104. double transmit message buffer host transitions transition host command condition description he mbccsr[2n+1].edt:= 1 mbccsr[2n+1].eds = 0 application triggers message buffer enable. hd mbccsr[2n+1].eds = 1 application triggers message buffer disable. hl mbccsr[2n].lckt:= 1 mbccsr[2n].lcks = 0 application triggers message buffer lock. hu mbccsr[2n].lcks = 1 application triggers message buffer unlock. table 3-103. double transmit message buffer state description (transmit side) (sheet 2 of 2) state mbccsrn access region description eds lcks appl. module flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 173 transition priorities the application can trigger only one transition at a time. there is no need to specify priorities among them. as shown in the first part of table 3-106 , the module transitions have a high er priority than the application transitions. the priorities among th e flexray module transitions and th e related states are given in the second part of table 3-106 . these priorities apply only to the tran smit side. the internal message transmit start transition is has tho lowest priority. table 3-105. double transmit message buffer module transitions transition condition description common transitions is see section 3.4.6.4.5, ?internal message transfer i nternal message transfer s tart - start transfer of message data from commit side to transmit side. ie i nternal message transfer e nd - stop transfer of message data from commit side to transmit side. note: the internal message transfer is st opped before the slot or segment start. transmit side specific transitions sa slot match and static slot s lot a ssigned - message buffer is assigned to next static slot. ma slot match and cyclecounter match m essage a vailable - message buffer is assigned to next slot and cycle counter filter matches. tx slot start and mbccsr[2n+1].cmt = 1 t ransmission slot start - slot start and commit bit cmt is set. in case of a dynamic slot, platesttx is not exceeded. su status updated s tatus u pdated - slot status field and messa ge buffer status flags updated. interrupt flag set. sts static slot start st atic slot s tart - start of static slot. dss dynamic slot start or symbol window start or nit start d ynamic slot or s egment s tart. - start of dynamic slot or symbol window or nit. sss slot start or symbol window start or nit start s lot or s egment s tart - start of static slot or dy namic slot or symbol window or nit. table 3-106. double transmit message buffer transition priorities state priority description module vs. application idle is > hd is > hl internal message transfer start > message buffer disable internal message transfer start > message buffer lock module internal idle ma > sa message available > slot assigned ccma tx > sts tx > dss transmission slot start > static slot start transmission slot start > dynamic slot start flexray module (flexrayv2) mfr4300 data sheet, rev. 3 174 freescale semiconductor 3.4.6.4.4 message preparation the application provides the message data through the commit side. the transmission itself is executed from the transmit side. the transfer of the message data from the commit side to th e transmit side is done by the internal message transfer , which is described in section 3.4.6.4.5, ?internal message transfer to transmit a message over the flex ray bus, the application writes the message data into the message buffer data field of the commit side and sets the commit bit cmt in the message buffer configuration, control, status registers (mbccsrn) . the physical access to the message buffer data field is described in section 3.4.3.1, ?individual message buffers ?. as indicated by table 3-102 , the application shall write to the me ssage buffer data field and change the commit bit cmt only if the transmit messa ge buffer is in one of the states hdis, hdislck, or hlck . the application can change the state of a message buffe r if it issues the appropriate commands given in table 3-104 . the state change is indica ted through the mbccsrn.eds a nd mbccsrn.lcks status bits. 3.4.6.4.5 internal message transfer the internal message transfer transf ers the message data from the commit side to the transmit side. the internal message transfer is implemented as the swapping of the content of the message buffer index registers (mbidxrn) of the commit side and the transmit si de. after the swapping, the commit side cmt bit is cleared, the commit side interrupt flag mbif is set, the transmit side cmt bit is set, and the transmit side dval bit is cleared. the conditions and the point in time when the internal message transfer is started are controlled by the message buffer commit mode bit mcm in the message buffer configuration, control, status registers (mbccsrn) . the mcm bit configures the me ssage buffer for either the st reaming commit mode or the immediate commit mode. a detail ed description is given in streaming commit mode and immediate commit mode . the internal message transfer is triggered with the transition is . both sides of the message buffer enter enter one of the cc itx states. the internal message transf er is finished wi th the transition ie . streaming commit mode the intention of the streaming commit mode is to ensure that each committed message is transmitted at least once . the flexray module will not st art the internal message transf er for a message buffer as long as the message data on the transmit si de is not transmitted at least once. the streaming commit mode is conf igured by clearing the message buffer commit mode bit mcm in the message buffer configuration, cont rol, status registers (mbccsrn) . in this mode, the internal message tr ansfer from the commit side to the transmit side is started for a double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data are valid, i.e. mbccsr[2n].cmt = 1 3. the transmit side is in one of the states idle , ccsa , or ccma 4. the transmit side contains either no vali d message data, i.e. mbccsr[2n+1].cmt = 0 or the message data were tr ansmitted at least once, i.e. mbccsr[2n+1].dval = 1 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 175 an example of a streaming commit mode state change diagram is given in figure 3-125 . in this example, both the commit and the transmit si de do not contain valid message data and the a pplication provides two messages. the message buffer does not match the next slot. figure 3-125. internal message transfer in streaming commit mode immediate commit mode the intention of the immediate co mmit mode is to transmit the latest data provided by the application. this implies that it is not guaranteed that each pr ovided message will be tr ansmitted at least once. the immediate commit mode is configured by setti ng the message buffer commit mode bit mcm in the message buffer configuration, cont rol, status registers (mbccsrn) . in this mode, the internal message transfer from the commit side to the transmit side is started for one double transmit message buffer when all of the following conditions are fulfilled 1. the commit side is in the idle state 2. the commit site message data are valid, i.e. mbccsr[2n].cmt = 1 3. the transmit side is in one of the states idle , ccsa , or ccma it is not checked whether the transm it side contains no valid message data or valid message data were transmitted at least once. if message data are va lid and not transmitted, th ey may be overwritten. an example of a streaming commit mode state change diagram is given in figure 3-126 . in this example, both the commit and the tran smit side do not contain valid message data, and the applic ation provides two messages and the first message is gets overwritte n. the message buffer does not match the next slot. figure 3-126. internal message transfer in immediate commit mode idle commit tr a n s m i t idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu ccitx idle is ccitx ie idle hl hlck hu idle idle no internal message transfer, until message transmitted idle commit tr a n s m i t idle hl hlck side side slot s slot s+1 slot s+2 search[s+1] slot start slot start slot start hu ccitx idle is ccitx ie idle hl hlck hu idle ccitx idle is ccitx ie idle idle internal message transfer overwrites non-transmitted message flexray module (flexrayv2) mfr4300 data sheet, rev. 3 176 freescale semiconductor 3.4.6.4.6 message transmission for double transmit message buffers, the message buffer search checks only the transmit side part. the internal scheduling ensures, that the internal message transfer is stopped on the me ssage buffer search start. thus, the transmit side of message buffer, that is not in its transmis sion or status update slot, is always in the idle state. the message transmit behavior and transmission state changes of the transmit side of a double transmit message buffer are the same as for si ngle buffered transmit buffers, except that the transm it side of double buffers can not be locked by the application, i.e. the hu and hl transition do not exist. therefore, refer to section 3.4.6.2.5, ?message transmission? 3.4.6.4.7 message buffer status update the message buffer status u pdate behavior of the tran smit side of a double transm it message buffer is the same as for single transmit message buffers which is described in section 3.4.6.2.7, ?message buffer status update?. additionally, the slot status field of the commit side is update after the update of the sl ot status field of the transmit side, even if the commit side is locked by th e application. this is implem ented to provide the slot status of the most r ecent transmission slot. 3.4.7 individual message buffer search this section provides a detailed descripti on of the message buffer search algorithm. the message buffer search checks all enabled individua l message buffer to determine if a certain slot is assigned to this node for transmissi on or if this node is subscribed to a certain slot for reception. the message buffer search is a sequential algorithm and is started at the following protocol related events: ? each nit start ? each slot start in th e static frame segment ? each minislot start in the dynamic frame segment the search within the nit searches for message buffers assigned or subscribed to slot 1. the search within slot n searches for message buffers a ssigned or subscribed to slot n+1 . if the message buffer search is running while the ne xt message buffer search start event appears, the message buffer search is stopped and the message bu ffer search error flag msb_ef is set in the chi error flag register (chierfr) . this appears only if the chi freque ncy is to low to search through all message buffers within the nit or a minislot. the messa ge buffer result is not defined in this case. for more details see section 3.5.2, ?number of us able message buffers?. the filters criteria used for the message buffer search described in section 3.4.7.1, ?individual message buffer filtering ?. for double transmit message buffers only the transmit side is included in the search. during the search, a list of all ma tching message buffers is created. if all message buffers assigned or subscribed to the next slot are assigned to only one ch annel, then two lists of matching message buffer will be created, one for each channel. if all message buffers assigned or subscribed to the next slot are assigned to both channels, only one sorted list of matching message buffers is created. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 177 each message buffer list is sorted according to the priorities given in table 3-107 . from the group with the highest priority, the message buffer with the lowest message buffer numbe r is selected. for this message buffer the corresponding transition given in table 3-107 is triggered as the re sult of the message buffer search. 3.4.7.1 individual message buffer filtering the message buffer search identifies the matching message buffers by applying two individual message buffer filter. the first filter is the frame id filter, the second fi lter is the cycle count filter. 3.4.7.1.1 message buff er frame id filtering the message buffer frame id filter is used to dete rmine if the message buffe r can be considered for reception or transmission in a certain slot on a per channel basis. the frame id filter matches for a messa ge buffer with message buffer number n and the search slot s , if the value of the fid field in the message buffer frame id registers (mbfidrn) equals s. only message buffer with a frame id filter match ma y appear in the matching message buffer list. all transmit message buffer with a matc hing frame id will appear in the matching message buffer list. only receive message buffer with a matchi ng frame id and a matching cycle count er filter will appear in the matching message buffer list. 3.4.7.1.2 message buffer cycle counter filtering the message buffer cycle counter filter is a valu e-mask filter defined by the ccfe, ccfmsk, and ccfval fields in the message buffer cycle counter filter registers (mbccfrn) . this filter determines a set of communication cycles in which the message buf fer is considered for message reception or message transmission. if the cycle count er filter is disabled, i.e. ccfe = ?0?, this set of cycles consists of all communication cycles. if the cycle counter filter of a message buffer does not match a certain communication cycle number, this message buffer is not considered for message transmi ssion or reception in that communication cycle. in case of a transmit messag e buffer, though, this buffer is added to the matching message buffer list with table 3-107. message buffer search priority priority mbccsrn description transition mtd lcks cmt ccfm 1 1 cycle counter filter match, see section 3.4.7.1.2, ?message buffer cycle counter filtering? (highest) 0 1011transmit buffer, unlocked, committed, matches cycle c ount ma 1 1001 transmit buffer, locked or uncommitted, matches cycle count sa 11x1 sa 2 1 x x 0 transmit buffer, assigned to slot sa 30001 receive buffer, unlocked, matches cycle count sb (lowest) 40111receive buffer, locked, matches cycle count sb flexray module (flexrayv2) mfr4300 data sheet, rev. 3 178 freescale semiconductor ccfm = ?0? to indicate the sl ot assignment and to trigge r the null frame transmission. in case of an receive message buffer, this buffer is not added to the matchi ng message buffer list. a message buffer matches it s cycle counter filter for the communica tion cycle with the number ccn if at least one of the following conditions evaluates to true: eqn. 3-8 eqn. 3-9 3.4.7.1.3 message buffer c hannel assignment consistency the message buffer channel assignment given by the cha and chb bits in the message buffer cycle counter filter re gisters (mbccfrn) defines the channels on which the message buffer will receive or transmit. the message buffer with number n transmits or receives on ch annel a if mbccfrn.cha = ?1? and transmits or receives on ch annel b if mbccfrn.chb = ?1?. to ensure correct message buffer operation, all messag e buffers assigned to the same slot must have a consistent channel assignment. that means that all message buffers assigned to the same slot must be either assigned to only one channel, or assigned to both channels. the behavior of the message buffer search is not defined, if both type s of channel assignments occur for one slot. an inconsistent channel assignment for message buffer 0 and message buffer 1 is depicted in figure 3-127 . figure 3-127. inconsistent channel assignment 3.4.8 individual message buffer reconfiguration the initial configuration of each i ndividual message buffer can be changed even when the protocol is not in the poc:config state. this is referred to as individual message buffer reconfiguration . the configuration bits and fiel ds that can be changed ar e given in the section on specific configuration data . the common configuration data given in the section on specific configuration data can not be reconfigured when the protocol is out of the poc:config state. 3.4.8.1 reconfiguration schemes depending on the target and destinatio n basic state of the message buffer th at is to be reconfigured, there are three reconfiguration schemes. 3.4.8.1.1 basic type not changed (rc1) a reconfiguration will not change the basic type of the individual message buffer, if both the message buffer transfer direction bit mbccsn.mtd and th e message buffer type bit mbccsn.mbt are not changed. this type of reconfi guration is denoted by rc1 in figure 3-128 . single transmit and receive mbccfrn.ccfe == 0 ccn[5:0] & mbccfrn.ccfmsk[5:0] == mb ccfrn.ccfval[5:0] & mbccfrn.ccfmsk[5:0] mb0 mbccfr0.cha = 1, mbccfr0.chb = 0 mb1 dual channel assignment single channel assignment mbfidr0.fid = 10 mbfidr1.fid = 10 mbccfr1.cha = 1, mbccfr1.chb = 1 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 179 message buffers can be rc1- reconfigured when in the hdis or hdislck state. double transmit message buffers can be rc1-reconfigured if both the transmit side and the commit side are in the hdis state. 3.4.8.1.2 buffer type not changed (rc2) a reconfiguration will not change the buffer type of the individual me ssage buffer if the message buffer buffer type bit mbccsrn.mbt is not changed. this type of reconfiguration is denoted by rc2 in figure 3-128 . it applies only to single transmit and receive message buffers. single transmit and receive message buffers can be rc2-reconfigured when in the hdis or hdislck state. 3.4.8.1.3 buffer type changed (rc3) a reconfiguration will change the buffer type of th e individual message buffer if the message buffer type bit mbccsrn.mbt is changed. this type of reconfigurat ion is denoted by rc3 in figure 3-128 . the rc3 reconfiguration splits one double buffer into two single buffers or combines two single buffer into one double buffer. in the later case, the two single messa ge buffers must have consecutive message buffer numbers and the smaller one must be even. message bu ffers can be rc3 reconfigured if they are in the hdis state. figure 3-128. message buffer reconfiguration scheme 3.4.9 receive fifo this section provides a detailed de scription of the two receive fifos. 3.4.9.1 overview the receive fifos implement the que ued receive buffer defined by the flexray communications system protocol specification, version 2.1. one receive fifo is assigned to ch annel a, the other receive fifo is assigned to channel b. both fifos work completely independent from each other. the message buffer structure of each fifo is described in section 3.4.3.3, ?receive fifo?. the area in the frm for each of the two recei ve fifos is characterized by: ? the index of the first fifo entry given by receive fifo start i ndex register (rfsir) ? the number of fifo entries and the le ngth of each fifo entry as given by receive fifo depth and size register (rfdsr) single rx single tx double tx (commit side) double tx (transmit side) rc1 rc1 rc1 rc2 rc3 rc3 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 180 freescale semiconductor 3.4.9.2 receive fifo configuration the receive fifo control and c onfiguration data are given in section 3.4.3.7, ?receive fifo control and configuration data?. the configuration of the receive fifos consists of two steps. the first step is the allocation of the required am ount of frm for the flexray window. this includes the allocation of the message buffer header area and the allocation of the message buffer data fields. for more details see section 3.4.4, ?flexray memory layout?. the second step is the programming of the confi guration data register while the pe is in poc:config. the following steps configur e the layout of the fifo. ? the number of the first message buf fer header index that belongs to the fifo is written into the receive fifo start i ndex register (rfsir) . ? the depth of the fifo is written into the fifo_depth field in the receive fifo depth and size register (rfdsr) . ? the length of the message buffer data field for the fifo is writ ten into the entry_size field in the receive fifo depth and size register (rfdsr) . note to ensure, that the read index rdidx always points to a message buffer that contains valid data, the receive fi fo must have at least 2 entries. the fifo filters are configured through the fifo f ilter registers. 3.4.9.3 receive fifo reception the frame reception to the receive fifo is enabled, if for a certain slots no message buffer is assigned or subscribed. in this case the fifo filter path shown in figure 3-129 is activated. when the receive fifo filter path indicates that the received frame must be appended to the fifo, the flexray module writes the received frame header and slot status into the message buffer header field indicated by the internal fi fo header write index. the payload data are written in the message buffer data field. if the status of the received frame indicates a valid frame, the in ternal fifo header write index is updated and the fifo not-empty inte rrupt flag fneaif/fnebif in the global interrupt flag and enable register (gifer) is set. 3.4.9.4 receive fifo message access if the fifo not-empty interrupt flag fneaif/fnebif in the global interrupt flag and enable register (gifer) is set, the receive fifo contains valid re ceived messages, which can be accessed by the application. the receive fifo does not require locking to ac cess the message buffers. to access the message the application first reads the receiv e fifo read index rdidx from the receive fifo a read index register (rfarir) or receive fifo b read index register (rfbrir) , respectively. this index points to the message buffer header field of the ne xt message buffer that contains va lid data. the application can access the message data as described in section 3.4.3.3, ?receive fifo?. when the application has read all message buffer data and status inform ation, it writes ?1? to the fifo not -empty interrupt flags fneaif or flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 181 fnebif. this clears the interrupt flag and updates the rdidx field in the receive fifo a read index register (rfarir) or receive fifo b read index register (rfbrir) , respectively.when the rdidx value has reached the last me ssage buffer header field th at belongs to the fifo, it wraps around to the index of the first message buffer header fi eld that belongs to the fifo. this value is provided by the sidx field in the receive fifo start i ndex register (rfsir) . 3.4.9.5 receive fifo filtering the receive fifo filt ering is activated after al l enabled individual receive message buffers have been searched without success for a message buffer to receive the current frame. the flexray module provides three sets of fifo filt ers. the fifo filters are applied to valid non-null frames only. the fifo will not rece ive invalid or null-frames. for each fifo filter, the pass criteria is specified in the related section given below. only fram es that have passed all filters will be appended to the fifo. the fifo filter path is depicted in figure 3-129 . flexray module (flexrayv2) mfr4300 data sheet, rev. 3 182 freescale semiconductor figure 3-129. received frame fifo filter path a received frame passes the fifo filtering if it has passed all three type of filter. 3.4.9.5.1 rx fifo frame id value-mask rejection filter the frame id value-mask rejection filter is a value-mask filter and is defined by the fields in the receive fifo frame id rejection filt er value register (rffidrfvr) and the receive fifo frame id rejection filter mask register (rffidrfmr) . each received frame with a fram e id fid that does not match the value-mask filter value passes th e filter, i.e. is not rejected. consequently, a received valid frame with the frame id fid passes the rx fifo frame id value-mask rejection filter if equation 3-10 is fulfilled. eqn. 3-10 valid frame received ( vrf ) individual message buffer found no store into message buffer ( vrf ) frame id value-mask rejection filter passed ignore frame else frame id range rejection filter frame id range acceptance filter frame received in dynamic segment no message id acceptance filter no fifo full null frame ( vrf!header!nfindicator=?0? ) yes yes no passed else passed else yes message id ( vrf!header!ppindicator=?1? ) yes passed append to fifo ( vrf ) no yes set fifo overflow interrupt flag else fid & rffidrfmr.fidrfmsk != rffi drfvr.fidrfval & rffidrfmr.fidrfmsk flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 183 the rx fifo frame id value-mask re jection filter can be c onfigured to pass all frames by the following settings. ? rffidrfvr.fidrfval:= 0x000 and rffidrfmr.fidrfmsk:= 0x7ff using the settings above, only the frame with frame id 0 will be rejected, which is an invalid frame. all other frames will pass. the rx fifo frame id value-mask rejection filter can be configured to reject all frames by the following settings. ? rffidrfmr.fidrfmsk:= 0x000 using the settings above, equation 3-10 can never be fulfilled (0!= 0) a nd thus all frames are rejected; no frame will pass. this is the reset value for the rx fifo. 3.4.9.5.2 rx fifo frame id range rejection filter each of the four rx fifo frame id range filters can be configured as a rejection filter. the filters are configured by the receive fifo range filter conf iguration register (rfrfcfr) and controlled by the receive fifo range filter control register (rfrfctr) . the rx fifo frame id range filters apply to all received valid frames. a received frame with th e frame id fid passes the rx fifo frame id range rejection filters if either no rejection filter is enabled, or, for all of the enabled rx fi fo frame id range rejection filters, i.e. rfrfctr. fimd = 1 and rfrfctr.fien = 1, equation 3-11 is fulfilled. eqn. 3-11 consequently, all frames with a frame id that fulfills equation 3-12 for at least one of the enabled rejection filters will be reject ed and thus not pass. eqn. 3-12 3.4.9.5.3 rx fifo frame id range acceptance filter each of the four rx fifo frame id range filter s can be configured as an ac ceptance filter. the filters are configured by the receive fifo range filter conf iguration register (rfrfcfr) and controlled by the receive fifo range filter control register (rfrfctr) . the rx fifo frame id range filters apply to all received valid frames. a received frame with th e frame id fid passes the rx fifo frame id range acceptance filters if either no acceptance filter is enable d, or, for at least one of the enabled rx fifo frame id range acceptance filters, i.e. rf rfctr.fimd = 0 and rfrfctr.fien = 1, equation 3-13 is fulfilled. eqn. 3-13 3.4.9.5.4 rx fifo messa ge id acceptance filter the rx fifo message id acceptance filter is a value-mask filter and is defined by the receive fifo message id acceptance filter value register (rfmidafvr) and the receive fifo message id acceptance filter mask register (rfmiafmr) . this filter applies only to valid frames received in the dynamic segment with the payload pream ble indicator bit ppi set to ?1?. all other frames will pass this filter. fid < rfrfcfri.sid(0) and rfrfcfri.sid(1) < fid rfrfcfri.sid(0) <= fid <= rfrfcfri.sid(1) rfrfcfri.sid(0) <= fid <= rfrfcfri.sid(1) flexray module (flexrayv2) mfr4300 data sheet, rev. 3 184 freescale semiconductor a received valid frame in the dynamic segment with the payload preamble indicator bit ppi set to ?1? and with the message id mid (the first two bytes of the payload) will pass the rx fifo message id acceptance filter if equation 3-14 is fulfilled. eqn. 3-14 the rx fifo message id acceptance filter can be configured to accep t all frames by setting ? rfmidafmr.midafmsk:= 0x000 using the settings above, equation 3-14 is always fulfilled a nd all frames will pass. 3.4.10 channel device modes this section describes the two fl exray channel device modes that are supported by the flexray module. 3.4.10.1 dual channel device mode in the dual channel device mode, both flexray ports are connected to physical flexray bus lines. the flexray port consisting of rxd_ bg1, txd_bg1, and txen1# is connected to the physical bus channel a and the flexray port consisting of rxd_bg2, tx d_bg2, and txen1# is conne cted to the physical bus channel b. the dual channel system is shown in figure 3-130 . figure 3-130. dual channel device mode 3.4.10.2 single channel device mode the single channel device mode suppor ts devices that have only one flex ray port available. this flexray port consists of the signals rxd_bg1, txd_bg1, a nd txen1# and can be connected to either the physical bus channel a (shown in figure 3-131 ) or the physical bus channel b (shown in figure 3-132 ). mid & rfmidafmr.midafmsk = rfmidafv r.midafval & rfmidafmr.midafmsk chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel 0 channel 1 flexray channel a flexray bus driver channel a rxd_bg1 txd_bg1 txen1# flexray channel b flexray bus driver channel b rxd_bg2 txd_bg2 txen2# flexray module flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 185 if the device is configured as a single channel device by setting mcr.scd to ?1?, only the internal channel a and the flexray port a is used. depending on the setting of mcr.cha and mcr.chb, the internal channel a behaves either as a flex ray channel a or flexray channel b. the bit mcr.cha must be set, if the flexray port a is connected to a flexray cha nnel a. the bit mcr.chb must be set if the flexray port a is connected to a flexray ch annel b. the two flexray channels di ffer only in the initial value for the frame crc ccrcinit . for a single channel device, the appli cation can access and configure only the registers related to internal channel a. figure 3-131. single channel device mode (channel a) figure 3-132. single channel device mode (channel b) chi pe cfg(a) reg(a) ccrcinit[a] ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel a flexray bus driver channel a rxd_bg1 txd_bg1 txen1# rxd_bg2 txd_bg2 txen2# flexray module chi pe cfg(a) reg(a) ccrcinit[b] cfg(b) reg(b) channel a channel b flexray channel b init value for frame crc is ccrcinit[b] ccrcinit[a] flexray bus driver channel a rxd_bg1 txd_bg1 txen1# rxd_bg2 txd_bg2 txen2# flexray module flexray module (flexrayv2) mfr4300 data sheet, rev. 3 186 freescale semiconductor 3.4.11 external clock synchronization the application of the external rate and offset correct ion is triggered when the application writes to the eoc_ap and erc_ap fields in the protocol operation c ontrol register (pocr) . the pe applies the external correction values in the next even-odd cycle pair as shown in figure 3-133 and figure 3-134 . if the offset correction applied in the nit of cycle 2n +1 shall be affect by the external offset correction, the eoc_ap field must be written to after the start of cycle 2n and before the end of the static segment of cycle 2n+1. if this field is written to after the end of the st atic segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycl e 2n+1. if the value is not applied in cycle 2n+1, then the value will be applied in the cycle 2n+3. refer to figure 3-133 for timing details. figure 3-133. external offset correction write and application timing if the rate correction for the cycle pair [2n+2, 2n+3] shall be affect by the external offset correction, the erc_ap field must be written to after the start of cy cle 2n and before the end of the static segment start of cycle 2n+1. if this field is written to after the end of the static segment of cycle 2n+1, it is not guaranteed that the external correction value is applied in cycle pair [2n+2, 2n+3]. if the valu e is not applied for cycle pair [2n+2, 2n+3], then the va lue will be applied for cycl e pair [2n+4, 2n+5]. refer to figure 3-134 for details. figure 3-134. external rate correct ion write and application timing 3.4.12 sync frame id and sync frame deviation tables the flexray protocol requires the pr ovision of a snapshot of the synchr onization frame id tables for the even and odd communication cycle fo r both channels. the flexray modul e provides the means to write a copy of these internal tables into the frm and ensures application access to consis tent tables by means of table locking. once the application has locked th e table successfully, the flexray module will not overwrite these tables and the applicat ion can read a consistent snapshot. note only synchronization frames that have passed the synchronization frame filters are considered for clock synchr onization and appear in the sync frame tables. static segment nit static segment nit eoc_ap write window eoc_ap application cycle 2n cycle 2n+1 static segment nit erc_ap write window erc_ap application cycle 2n static segment nit cycle 2n+1 static segment nit cycle 2n+2 static segment nit cycle 2n+3 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 187 3.4.12.1 sync frame id table content the sync frame id table is a snapshot of the protocol related variables vssyncidlista and vssyncidlistb for each even and odd communication cycle. this table provides a list of the frame ids of the synchronization frames received on the corresponding channel and cycle that are used for the clock synchronization. 3.4.12.2 sync frame deviation table content the sync frame deviation table is a snapshot of th e protocol related variable zsdev(id)(oe)(ch)!value. each sync frame deviation table entry provides the deviation value for the s ync frame, with the frame id presented in the corresponding en try in the sync frame id table. figure 3-135. sync table memory layout 3.4.12.3 sync frame id and sync frame deviation table setup the flexray module writes a copy of the internal sync hronization frame id and de viation tables into the frm if requested by the ap plication. the application must provide the appropria te amount of frm for the tables. the memory layout of the tables is given in figure 3-135 . each table occupies 120 16-bit entries. while the protocol is in poc:config state, the application must program the offsets for the tables into the sync frame table offset register (sftor) . sftor sftor + 180 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 sftor + 60 sftor +120 sync frame id cha 1 sync frame id cha 2 sync frame id cha 3 sync frame id cha 4 sync frame id cha 5 sync frame id cha 6 sync frame id cha 7 sync frame id cha 8 sync frame id cha 9 sync frame id cha 10 sync frame id cha 11 sync frame id cha 12 sync frame id cha 13 sync frame id cha 14 sync frame id cha 15 sync deviation cha 1 sync deviation cha 2 sync deviation cha 3 sync deviation cha 4 sync deviation cha 5 sync deviation cha 6 sync deviation cha 7 sync deviation cha 8 sync deviation cha 9 sync deviation cha 10 sync deviation cha 11 sync deviation cha 12 sync deviation cha 13 sync deviation cha 14 sync deviation cha 15 offset + $00 offset + $02 offset + $04 offset + $06 offset + $08 offset + $0a offset + $0c offset + $0e offset + $10 offset + $12 offset + $14 offset + $16 offset + $18 offset + $1a offset + $1c sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 sync frame id chb 1 sync frame id chb 2 sync frame id chb 3 sync frame id chb 4 sync frame id chb 5 sync frame id chb 6 sync frame id chb 7 sync frame id chb 8 sync frame id chb 9 sync frame id chb 10 sync frame id chb 11 sync frame id chb 12 sync frame id chb 13 sync frame id chb 14 sync frame id chb 15 sync deviation chb 1 sync deviation chb 2 sync deviation chb 3 sync deviation chb 4 sync deviation chb 5 sync deviation chb 6 sync deviation chb 7 sync deviation chb 8 sync deviation chb 9 sync deviation chb 10 sync deviation chb 11 sync deviation chb 12 sync deviation chb 13 sync deviation chb 14 sync deviation chb 15 offset + $1e offset + $20 offset + $22 offset + $24 offset + $26 offset + $28 offset + $2a offset + $2c offset + $2e offset + $30 offset + $32 offset + $34 offset + $36 offset + $38 offset + $3a sfcntr sfeva sfevb sfcntr sfoda sfodb even odd even odd flexray module (flexrayv2) mfr4300 data sheet, rev. 3 188 freescale semiconductor 3.4.12.4 sync frame id and sync frame deviation table generation the application controls the genera tion process of the sync frame id and sync frame deviation tables into the frm using the sync frame table configuration, cont rol, status register (sftccsr) . a summary of the copy modes is given in table 3-108 . the sync frame table generation pro cess is described in the following for the even cycle. the same sequence applies to the odd cycle. if the application has enabled the sync frame tabl e generation by setting sftccsr.siden to ?1?, the flexray module starts the update of the even cycle related tables after the start of the nit of the next even cycle. the flexray module checks if the application has lo cked the tables by r eading the sftccsr.elks lock status bit. if this bit is set, the flexray module will not update the ta ble in this cycle. if this bit is cleared, the flexray module locks this table and starts the table update. to indicate that these tables are currently updated and may contain inc onsistent data, the flexray module cl ears the even table valid status bit sftccsr.eval. once all table entr ies related to the even cycle have been transferred into the frm, the flexray module sets the even table valid bi t sftccsr.eval and the even cycle table written interrupt flag evt_if in the protocol interrupt flag register 1 (pifr1) . if the interrupt enable flag evt_ie is set, an interrupt request is generated. to read the generated tables, the application must lock the tables to prevent the flexray module from updating these tables. the locking is initiated by writing a ?1? to the even table lock trigger sftccsr.elkt. when the even table is not currently updated by the flexray module, the lock is granted and the even table lock status bit sftccsr.elks is set. this indicates that the application has successfully locked the even sync tables and the corresponding status informat ion fields sfra, sfrb in the sync frame counter register (sfcntr) . the value in the sftccsr.c ycnum field provides the number of the cycle that th is table is related to. the number of available table entries per chan nel is provided in the sfcntr.sfeva and sfcntr.sfevb fields. the application can now start to read the sync table data from the locations given in figure 3-135 . after reading all the data from the locked tables, th e application must unlock the table by writing to the even table lock trigger sftccsr.e lkt again. the even table lock status bit sftccsr.elks is reset immediately. table 3-108. sync frame table generation modes sftccsr description opt sdven siden 0 0 0 no sync frame table copy 0 0 1 sync frame id tables will be copied continuously 010reserved 0 1 1 sync frame id tables and sync frame deviation tables will be copied continuously 1 0 0 no sync frame table copy 1 0 1 sync frame id tables for next even-odd-cycle pair will be copied 010reserved 1 1 1 sync frame id tables and sync frame deviat ion tables for next even-odd-cycle pair will be copied flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 189 if the sync frame table generatio n is disabled, the table valid bi ts sftccsr.eval and sftccsr.eval are reset when the counter values in the sync frame counter register (sfcntr) are updated. this is done because the tables stored in the frm are no longer rela ted to the values in the sync frame counter register (sfcntr) . figure 3-136. sync frame table trigger and generation timing 3.4.12.5 sync frame table access the sync frame tables will be transferred into the frm dur ing the table write windows shown in figure 3-136 . during the table write, the appli cation can not lock the table that is currently written. if the application locks the table outsi de of the table write window, th e lock is granted immediately. 3.4.12.5.1 sync frame tabl e locking and unlocking the application locks the even/odd s ync frame table by writin g ?1? to the lock trigger bit elkt/olkt in the sync frame table configuration, cont rol, status register (sftccsr) . if the affected table is not currently written to the frm, the lo ck is granted immediately, and the lock status bit elks/olks is set. if the affected table is currently written to the frm, the lock is not granted. in this case, the application must issue the lock request again until the lock is granted. the application unlocks the even/odd sync frame table by writing ?1? to the lock trigger bit elkt/olkt. the lock status bit elks/olks is cleared immediately. 3.4.13 mts generation the flexray module provides a flexible means to request the transmission of the media access test symbol mts in the symbol window on channel a or channel b. the application can configure the se t of communication cycles in which the mts will be transmitted over the flexray bus by programming the cycc ntmsk and cyccntval fields in the mts a configuration regi ster (mtsacfr) and mts b configuration register (mtsbcfr) . the application enables or disables the generation of the mts on either channel by setting or clearing the mte control bit in the mts a configuration register (mtsacfr) or mts b configuration register (mtsbcfr) . if an mts is to be transmitted in a certai n communication cycle, the application must set the mte control bit during the static segm ent of the preceding communication cycle. the mts is transmitted over channel a in the communication cycle with number ccn, if equation 3-16 , equation 3-17 , and equation 3-17 are fulfilled. eqn. 3-15 eqn. 3-16 sftccsr.[opt,siden,sdven] write window even table write static segment nit static segment nit static segment nit cycle 2n-1 cycle 2n cycle 2n+1 odd table write psr0.protstate = normal_active mtsacfr.mte = 1 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 190 freescale semiconductor eqn. 3-17 the mts is transmitted over channel b in th e communication cycle wi th number ccn, if equation 3-15 , equation 3-18 , and equation 3-19 are fulfilled. eqn. 3-18 eqn. 3-19 3.4.14 sync frame and startup frame transmission the transmission of sync frames a nd startup frames is controlled by the following register fields: ? pcr18.key_slot_id: provides the number of the sl ot for sync or star tup frame transmission ? pcr11.key_slot_used_for_sync: indi cates sync frame transmission ? pcr11.key_slot_used_for_startup: i ndicates startup frame transmission ? pcr12.key_slot_header_crc: provides header crc for sync frame or startup frame ? message buffer with message buffer number n=pcr18.key_slot_id the generation of the sync or startup frames depends on the cu rrent protocol state. in the poc:startup state, the generation is independent of the message buffer setup; in the poc:normal active state, the generation is affected by the current message buffer setup. 3.4.14.1 sync frame and startup frame transmission in poc:startup in the poc:startup state, the sync and startup frame transmis sion is independent of the message buffer setup. if at least one of the indicatio n bits pcr11.key_slot_used_for_sync or pcr11.key_slot_used_for_startup is set, a null frame will be transmitted in the sl ot with slot number pcr18.key_slot_id. the header crc for this null frame is taken fr om pcr12.key_slot_header_crc. the settings of the sync and start up frame indicators are taken from pcr11.key_slot_used_for_sync and pcr11.key_slot_used_for_startup. 3.4.14.2 sync frame and startup frame transmission in poc:normal active in the poc:normal active state, the sync and startup frame tr ansmission depends on the message buffer setup. if at least one of the indicatio n bits pcr11.key_slot_used_for_sync or pcr11.key_slot_used_for_sta rtup is set, or if a transmit me ssage buffer with mbfidrn.fid == pcr18.key_slot_id is configured and enabled, a null fr ame or data frame will be transmitted in the slot with slot number pcr18.key_slot_id. the head er crc for this frame is taken from pcr12.key_slot_header_crc, the settings of the s ync and startup frame indicators are taken from pcr11.key_slot_used_for_sync and pc r11.key_slot_used_for_startup. a data frame will be transmitted if the message buffer is unlocked and committed and the cycle counter filter matches the current cycle. 3.4.15 sync frame filtering each received synchronization frame must pass the sync frame accept ance filter and the sync frame rejection filter before it is considered for clock synchronization. if the synchr onization frame filtering is cc n[5:0] & mtsacfr.ccfmsk[5:0]== mtsa cfr.ccfval[5:0] & mtsacfr.ccfmsk[5:0] mtsbcfr.mte = 1 cc n[5:0] & mtsbcfr.ccfmsk[5:0] = mt sbcfr.ccfval[5:0] & mtsbcfr.ccfmsk[5:0] flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 191 globally disabled, i.e. the sffe control bit in the module configuration register (mcr) is cleared, all received synchronization frames are considered for cl ock synchronization. if a received synchronization frame did not pass at least one of the two filters, this frame is processed as a normal frame and is not considered for clock synchronization. 3.4.15.1 sync frame acceptance filtering the synchronization frame accep tance filter is implemente d as a value-mask filter. the value is configured in the sync frame id acceptance filt er value register (sfidafvr) and the mask is configured in the sync frame id acceptance filt er mask register (sfidafmr) . a received synchr onization frame with the frame id fid passes the s ync frame acceptance filter, if equation 3-20 or equation 3-21 evaluates to true. eqn. 3-20 eqn. 3-21 note sync frames are transmitted in the static segment only. thus fid <= 1023. 3.4.15.2 sync frame rejection filtering the synchronization frame rejection filter is a comparator. the compare value is defined by the sync frame id rejection filte r register (sfidrfr) . a received synchronization fr ame with the frame id fid passes the sync frame rejection filter if equation 3-22 or equation 3-23 evaluates to true. eqn. 3-22 eqn. 3-23 note sync frames are transmitted in the static segment only. thus fid <= 1023. 3.4.16 strobe signal support the flexray module provides a number of strobe signa ls for observing internal protocol timing related signals in the protocol engine. the signals are listed and described in table 3-11 . 3.4.16.1 strobe signal assignment each of the strobe signals listed in table 3-11 can be assigned to one of th e four strobe ports using the strobe signal control register (stbscr) . to assign multiple strobe si gnals, the application must write multiple times to the strobe signal control register (stbscr) with appropriate settings. to read out the current settings for a strobe signal with number n, the application must execute the following sequence. 1. write to stbscr with wmd = 1 a nd sel = n. (updates sel field only) mcr.sffe == 0 fid 9 :0 [] & sfidafmr.fmsk[9:0] == sfidaf vr.fval[9:0] & sfidafmr.fmsk[9:0] mcr.sffe == 0 fid 9 :0 [] != sfidrfr.synfrid[9:0] flexray module (flexrayv2) mfr4300 data sheet, rev. 3 192 freescale semiconductor 2. read stbcsr. the sel field provides n and the enb and stbpse l fields provides the settings for signal n. 3.4.16.2 strobe signal timing this section provides detail ed timing information of the strobe signals with respect to th e protocol engine clock. the strobe signals display internal pe signals. due to the internal archit ecture of the pe, some signals are generated several pe clock cycles before the actual action is performe d on the flexray bus. these signals are listed in table 3-11 with a negative clock offset. an example waveform is given in figure 3-137 . figure 3-137. strobe signal timing (type = pulse, clk_offset = -2) other signals refer to events that occurred on the fl exray bus some cycles befo re the strobe signal is changed. these signals are listed in table 3-11 with a positive clock offset. an example waveform is given in figure 3-138 . figure 3-138. strobe signal timing (type = pulse, clk_offset = +4) 3.4.17 timer support the flexray module provides two timers, which run on the flexray time base. each timer generates a maskable interrupt when it reaches a c onfigured point in time. timer t1 is an absolute timer. timer t2 can be configured to be an absolute or a relative timer . both timers can be configured to be repetitive. in the non-repetitive mode, timer stops if it expires. in repetitive mode, timer is restarted when it expires. both timers are active only when the protocol is in poc:normal active or poc:normal passive state. if the protocol is not in one of these modes, the timers are stopped. the application must restart the timers when the protocol has reached the poc:normal active or poc:normal passive state. pe clock strobe signal flexray bus event -2 pe clock strobe signal flexray bus event +4 flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 193 3.4.17.1 absolute timer t1 the absolute timer t1 has the protoc ol cycle count and the macrotick c ount as the time base. the timer 1 interrupt flag ti1_if in the protocol interrupt flag register 0 (pifr0) is set at the macrotick start event, if equation 3-24 and equation 3-25 are fulfilled eqn. 3-24 eqn. 3-25 if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (pier0) is asserted, an interrupt request is generated. the status bit t1st is set when the timer is tri ggered, and is cleared when the timer expires and is non-repetitive. if the timer expires but is repetitive, the t1st bit is not cleared and the t imer is restarted immediately. the t1st is cleared when the timer is stopped. 3.4.17.2 absolute / relative timer t2 the timer t2 can be configured to be an absolute or relative timer by setting the t2_cfg control bit in the timer configuration and control register (ticcr) . the status bit t2st is set when the timer is triggered, and is cleared when the timer expire s and is non-repetitive. if the timer expires but is repetitive, the t2st bit is not cleared and the timer is restarted immediat ely. the t2st is cleared when the timer is stopped. 3.4.17.2.1 absolute timer t2 if timer t2 is configured as an absolute timer, it ha s the same functionality time r t1 but the configuration from timer 2 configuration register 0 (ti2cr0) and timer 2 configuration register 1 (ti2cr1) is used. on expiration of timer t2, the interrupt flag ti2_if in the protocol interrupt flag register 0 (pifr0) is set. if the timer 1 interrupt enable bit ti1_ie in the protocol interrupt enable register 0 (pier0) is asserted, an interrupt request is generated. 3.4.17.2.2 relative timer t2 if the timer t2 is configured as a relati ve timer, the interrupt flag ti2_if in the protocol interrupt flag register 0 (pifr0) is set, when the programmed amount of macroticks mt[31:0], defined by timer 2 configuration regi ster 0 (ti2cr0) and timer 2 configuration register 1 (ti2cr1) , has expired since the trigger or restart of timer 2. the re lative timer is implemented as a dow n counter and expires when it has reached 0. at the macrotick start event, the value of mt[31:0] is checked and then decremented. thus, if the timer is started with mt [31:0] == 0, it expires at the next macrotick start. 3.4.18 slot status monitoring the flexray module provides several means for slot st atus monitoring. all slot status monitors use the same slot status vector provided by the pe. the pe provi des a slot status vector for each static slot, for each dynamic slot, for the symbol window, and for the nit, on a per channel base. the content of the slot status vector is described in table 3-109 . the pe provides the slot status vector within the first macrotick after the end of the related slot/window/nit, as shown in figure 3-139 . cycctr.cyccnt & t1cysr.t1_cyc_msk == t1cysr.t1_cyc_val & t1cysr.t1_cyc_msk mtctr.mtct == ti1mtor.t1_mtoffset flexray module (flexrayv2) mfr4300 data sheet, rev. 3 194 freescale semiconductor figure 3-139. slot status vector update note the slot status for the nit of cycle n is provided after the start of cycle n+1. table 3-109. slot status content status content static / dynamic slot slot related status vss!validframe - valid frame received vss!syntaxerror - syntax error occu rred while receiving vss!contenterror - content error occu rred while receiving vss!bviolation - boundary violation while receiving for slots in which th e module transmits: vss!txconflict - reception ongoing while transmission starts for slots in which the module does not transmit: vss!txconflict - reception ongoing while transmission starts first valid - channel that has received the first valid frame received frame related status extracted from a) header of valid frame, if vss!validframe = 1 b) last received header, if vss!validframe = 0 c) set to ?0?, if nothing was received vrf!header!nfindicator - null frame indicator (0 for null frame) vrf!header!sufindicator - startup frame indicator vrf!header!syfindicator - sync frame indicator cycle start slot start slot start symbol window start mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 195 3.4.18.1 channel status error counter registers the two channel status error counter registers, channel a status error co unter register (casercr) and channel b status error co unter register (cbsercr) , incremented by one, if at least one of four slot status error bits, vss!syntaxerror , vss!contenterror , vss!bviolation , or vss!txconflict is set to ?1?. the status vectors for all slots in the static and dynami c segment, in the symbol window, and in the nit are taken into account. the counter s wrap round after they have reached the maximum value. 3.4.18.2 protocol status registers the protocol status register 2 (psr2) provides slot status information about the network idle time nit and the symbol window. the protocol status register 3 (psr3) provides aggregated slot status information. 3.4.18.3 slot status registers the eight slot status registers, slot status registers (ssr0?ssr7) , can be used to observe the status of static slots, dynamic slots, the symbol window, or the nit without individual message buffers. these registers provide all slot status re lated and received frame / symbol relate d status information, as given in table 3-109 , except of the first valid indicator for non-transmission slots. 3.4.18.4 slot status counter registers the flexray module provides four slot status error counter registers, slot status counter registers (sscr0?sscr3) . each of these slot status c ounter registers is updat ed with the value of an internal slot status counter at the start of a comm unication cycle. the internal slot st atus counter is incremented if its increment condition, defined by the slot status counter c ondition register (ssccr) , matches the status symbol window window related status vss!validframe - always 0 vss!contenterror - content error occu rred while receiving vss!syntaxerror - syntax error occu rred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - reception ongoing while transmission starts received symbol related status vss!validmts - valid media test access symbol received received frame related status see static/dynamic slot nit nit related status vss!validframe - always 0 vss!contenterror - content error occu rred while receiving vss!syntaxerror - syntax error occu rred while receiving vss!bviolation - boundary violation while receiving vss!txconflict - always 0 received frame related status see static/dynamic slot table 3-109. slot status content status content flexray module (flexrayv2) mfr4300 data sheet, rev. 3 196 freescale semiconductor vector provided by the pe. all static slots, the sym bol window, and the nit status are taken into account. dynamic slots are excluded . the internal slot status count ing and update timi ng is shown in figure 3-140 . figure 3-140. slot status counting and sscrn update the pe provides the status of the nit in the first slot of the next cycle. due to these facts, the sscrn register reflects, in cycle n, the stat us of the nit of cycle n-2, and the status of all static slots and the symbol window of cycle n-1. the increment condition for each slot status counter c onsists of two parts, the frame related condition part and the slot related conditi on part. the internal slot status counter sscrn_int is increm ented if at least one of the conditions is fulfilled: 1. frame related condition: ? (ssccrn.vfr | ssccrn.syf | ssccrn.nuf | ssccrn.suf) // count on frame condition = ?1?; and ? ((~ssccrn.vfr | vss!validframe ) & // valid frame restriction (~ssccrn.syf | vrf!header!syfindicator ) & // sync frame indicator restriction (~ssccrn.nuf | ~ vrf!header!nfindicator ) & // null frame indicator restriction (~ssccrn.suf | vrf!header!sufindicator )) // startup frame indicator restriction = ?1?; note the indicator bits syf, nuf, and su f are valid only when a valid frame was received. thus it is required to set the vfr always, whenever count on frame condition is used. 2. slot related condition: ? ((ssccrn.statusmask[3] & vss!contenterror ) | // increment on content error (ssccrn.statusmask[2] & vss!syntaxerror ) | // increment on syntax error (ssccrn.statusmask[1] & vss!bviolation ) | // increment on boundary violation cycle start slot start slot start symbol window start mt status(nit) mt status(slot 1) status(slot k) mt status(slot n) mt nit start status(sym.win) mt cycle start status(nit) communication cycle static segment dynamic segment symbol window nit slot 1 mt incr. sscrn_int on error incr. sscrn_int on error sscrn:= sscrn_int sscrn_int not updated sscrn:= sscrn_int flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 197 (ssccrn.statusmask[0] & vss!txconflict )) // increment on transmission conflict = ?1?; if the slot status counter is in si ngle cycle mode, i.e. ssccr n.mcy = ?0?, the internal slot status counter sscrn_int is reset at each cycle start. if the slot status counter is in the multicycle mode, i.e. ssccrn.mcy = ?1?, the counter is not reset and incremented, until the maximum value is reached. 3.4.18.5 message buffer slot status field each individual message buffer and each fifo message buffer provides a slot status field, which provides the information shown in table 3-109 for the static/dynamic slot. the upda te conditions for the slot status field depend on the message buffer type. refer to the message buffer update sections in section 3.4.6, ?individual message buffer functional description ?. 3.4.19 interrupt support the flexray module provides 172 individual interrupt sources and five comb ined interrupt sources. 3.4.19.1 individual interrupt sources 3.4.19.1.1 message buffer interrupts the flexray module provides 128 message buffer interrupt sources. each individual message buffer provides an interrupt flag mbccsn.mbif and an interrupt enable bit mbccsn.mbie. the flexray module sets the interrupt fl ag when the slot status of the message buffer was updated. if the interrupt enable bit is a sserted, an interrupt request is generated. 3.4.19.1.2 receive fifo interrupts the flexray module provides 2 r eceive fifo interrupt sources. each of the 2 receive fifo provide s a receive fifo not em pty interrupt flag. the flexray module sets the receive fifo not empty interrupt flag s (gifer.fnebif, gifer.fneaif) in the global interrupt flag and enable register (gifer) if the corresponding receive fifo is not empty. 3.4.19.1.3 wakeup interrupt the flexray module provides one interrupt source related to the wakeup. the flexray module sets the wakeup interrupt fl ag gifer.wupif when it has received a wakeup symbol on the flexray bus. th e flexray module generates an interrupt request if the interrupt enable bit gifer.wupie is asserted. 3.4.19.1.4 protocol interrupts the flexray module provides 25 interrupt sources for protocol related events. for details, see protocol interrupt flag register 0 (pifr0) and protocol interrupt flag register 1 (pifr1) . each interrupt source has its own interrupt enable bit. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 198 freescale semiconductor 3.4.19.1.5 chi error interrupts the flexray module provides 16 inte rrupt sources for chi related error events. for details, see chi error flag register (chierfr) . there is one common interrupt enable bit gifer.chiie for all chi error interrupt sources. 3.4.19.2 combined interrupt sources each combined interrupt source generates an interrupt request only when at least one of the interrupt sources that is combined ge nerates an interrupt request. 3.4.19.2.1 receive message buffer interrupt the combined receive message buffe r interrupt request rbirq is generated when at least one of the individual receive message buffers generates an interr upt request mbxirq[n] and the interrupt enable bit gifer.rbie is set. 3.4.19.2.2 transmit message buffer interrupt the combined transmit message buffer interrupt reque st tbirq is generated when at least one of the individual transmit message buffers generates an interrupt request mb xirq[n] and the interrupt enable bit gifer.tbie is asserted. 3.4.19.2.3 protocol interrupt the combined protocol interrupt reque st prtirq is generated when at le ast one of the individual protocol interrupt sources generates an interrupt request and the interrupt enable bit gifer.prie is set. 3.4.19.2.4 chi error interrupt the combined chi error interrupt interrupt request chiirq is generated when at least one of the individual chi error interrupt sour ces generates an inte rrupt request and the interrupt enable bit gifer.chie is set. 3.4.19.2.5 module interrupt the combined module interrupt request mirq is generated if at least one of the combined interrupt sources generates an interrupt request and the interrupt enable bit gifer.mie is set. flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 199 figure 3-141. scheme of cascaded interrupt request interrupt sources interrupt signals mbxirq[n-1:0] mbccsr n .mbif n chixirq[15:0] chier[15:0] 16 prtxirq[31:16] pifr0[15:0] 16 prtxirq[15:0] pifr1[15:0] 16 rbirq chiirq prtirq gifer.fneaif fneairq gifer.wupif wupirq gifer.rbie mbccsr n .mtd receive tr a n s m i t gifer.prie gifer.wupie gifer.mie mbccsr n .mbie & pier0[15:0] pier1[15:0] or & & & gifer.chie & & n & or tbirq gifer.tbie & n or or & & gifer.fneaie gifer.fnebif fnebirq & gifer.fnebie & & n = # message buffers or gifer.rbif gifer.tbif gifer.prif gifer.chif gifer.mif mirq flexray module (flexrayv2) mfr4300 data sheet, rev. 3 200 freescale semiconductor figure 3-142. int_cc# generation scheme figure 3-143. scheme of combined interrupt flags or int_cc# mirq crsr.lvif crsr.cmif crsr.prif crsr.erif interrupt sources com bined interrupt flags mbccsr n .mbif n chier[15:0] pifr0[15:0] pifr1[15:0] gifer.fneaif gifer.wupif cifr.tbif cifr.chif cifr.prif mbccsr n .mtd receive tr a n s m i t or & & or cifr.rbif n or or gifer.fnebif n = # message buffers n or cifr.mif cifr.fneaif cifr.wupif cifr.fnebif flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 201 3.4.20 clock domain crossing the clock domain crossing module cdc implements the signal crossi ng from the chi clock domain to the pe clock domain and vice versa. the signal crossing logic is implemented as a three-stage pipe-line. two pipe-line stages are used for clock synchronization; the third st age is used for pulse generation. 3.4.20.1 clock domain crossing signal latency due to the clock domain crossing implementation, each si gnal from the pe to the ch i is delayed by at least two chi clock cycles and by at most three chi clock cycles. in terms of time, the signal latency time t lat for a given chi frequency f chi is eqn. 3-26 3.5 initialization information this section provides information for in itializing and using the flexray module. 3.5.1 flexray initialization sequence the full flexray module is re set with the hard reset. additionally, th e protocol engine is reset in the stop mode and as a result of the reset protocol command issued using the protocol operation control register (pocr) . the hard reset resets all internal registers and all registers in the flexray module memory map. the protocol engine reset resets only the registers in the protocol engine. all register s in memory are not reset. the following is an initi alization sequence applicable to th e flexray module after a hard reset 1. configure flexray module ? set the control bits in the module configuration register (mcr) 2. enable the flexray module ? set the men bit in the module configuration register (mcr) ? the flexray module enters the normal mode 3. configure the protocol engine ? write the config command in to the poccmd field of the protocol operation control register (pocr) ? write to the pcr[0:31] registers to set all protocol parameters. 4. configure the message buffers and fifos ? set the number of message buffers used and the message buffer segmentation in the message buffer segment size and util ization register (mbssutr) ? define the message buffer data size in the message buffer data size register (mbdsr) ? configure each message buf fer by setting the confi guration values in the message buffer configuration, control, status registers (mbccsrn) , message buffer cycle counter filter registers (mbccfrn) , message buffer frame id registers (mbfidrn) , message buffer index registers (mbidxrn) 2 f chi ------- - t lat 3 f chi ------- - ? flexray module (flexrayv2) mfr4300 data sheet, rev. 3 202 freescale semiconductor ? configure the receive fifos 5. start the flexray module as a flexray node ? write the ready protocol comma nd into the poccmd field of the protocol operation control register (pocr) ? now the flexray module enters the flexray protocol after this sequence, the flex ray module is configured as a flexray node and is ready to be integrated into the flexray cluster. 3.5.2 number of usable message buffers this section describes how to determine the number of message buffers that can be utilized at a given chi clock frequency f chi . the flexray module uses a sequential search to de termine the individual message buffers suitable for transmission or reception in the next slot. this search must be fini shed within one flexray slot. the shortest flexray slot is an empty dyna mic slot. an empty dynamic slot is a minislot and consists of at least two macroticks. the minimum length of a corrected macr otick is 39 t. the length of 1 t is 25 ns. this results in a minimum slot length of eqn. 3-27 the search engine is located in the chi and runs on the chi clock. the search engine searches one individual message buffer pe r clock cycle. for intern al status update and double buffer commit operations, and as a result of the clock domain crossing jitter, an additional amount of 10 clock cycles is required to ensure correct operation. for a given number of message buffers and for a given chi clock frequency f chi , this results in a search duration of eqn. 3-28 as mentioned above, each message buffer search must be finished within one slot. thus the following equation must be fulfilled eqn. 3-29 this results in the formula to determine the mi nimum required chi frequenc y for a given number of message buffers that can be utilized. eqn. 3-30 the minimum chi frequency for a selected se t of message buffer numbers is given in table 3-110 . table 3-110. minimum chi frequency examples # message buffers minimum f chi 32 21.54 mhz t slotmin 1.95 s25 ns t ------ - 39 t mt -------- - 2mt ?? == t search 1 f chi ------- - messagebuffers 10 + () ? = t search t slotmin f chi messagebuffers 10 + 1.95 s -------------------------------------------------------- - flexray module (flexrayv2) mfr4300 data sheet, rev. 3 freescale semiconductor 203 3.6 application information 3.6.1 shut down sequence this section describes a safe shut down sequence to stop the flexray module gra cefully. the main targets of this sequence are ? do not send invalid data on the flexray bus ? do not corrupt flexray bus and do not disturb ongoing communication ? finish all ongoing reception firstly, the application must di sable all message buffers by trigge ring the edt trigger bit in the message buffer configuration, control, status registers (mbccsrn) , until the eds flag is cleared by the flexray module. this ensures that no transmission is starte d by the flexray module. if all message buffers are disabled, the application issues the halt command to the pe using the protocol operation control register (pocr) . the pe then waits for the end of th e communication cycle and goes into the poc:halt state. the application can observe this st ate change in the protstate field of the protocol status register 0 (psr0) . 3.6.2 protocol control command execution this section considers the issues of the protocol control command execution. the application issues any of the protocol control commands listed in the poccmd field of table 3-15 by writing the command to the poccmd field of the protocol operation control register (pocr) . as a result the flexray module sets the bsy bit while the command is transf erred to the pe. when the pe has accepted the command, the bsy flag is clear ed. all commands are accepted by the pe. the pe maintains a protocol comma nd vector. for each command that wa s accepted by the pe, the pe sets the corresponding command bit in the protocol comm and vector. if a command is issued while the corresponding command bit is set, the command is not queued and is lost. if the command execution block of the pe is idle, it selects the next accepted protocol command with the highest priority from the current protocol command vector according to the protocol control command priorities given in table 3-111 . if the current protocol state does not allow the execution of this protocol command (see poc state changes in flexray communications syst em protocol specification, version 2.1 ) the flexray module asserts the illegal protoc ol command interrupt flag ipc_if in the protocol interrupt flag register 1 (pifr1) . the protocol command is not executed in this case. some protocol commands may be inte rrupted by other commands or the de tection of a fatal protocol error as indicated by table 3-111 . if the application issues the reset, freeze, or ready command, or if the 64 37.95 mhz 128 70.77 mhz table 3-110. minimum chi frequency examples # message buffers minimum f chi flexray module (flexrayv2) mfr4300 data sheet, rev. 3 204 freescale semiconductor the pe detects a fatal protocol error, some comma nds already stored in the command vector will be removed from this vector. 3.6.3 protocol reset command the section considers the issues of the protocol reset command. the application issues the protoc ol reset command by writing the reset command code to the poccmd field of the protocol operation control register (pocr) . as a result, the pe stops its operation immediately, the flexray bus ports put into their idle state, and no mo re data or status information is sent to the chi. the lack of pe signals stops all mess age buffer operations in the chi. in particular, the message buffers that are currently unde r internal use remain internally locked. to overcome this message buffer internal lock situat ion, the application must put the protocol into the poc:default config state. this will release all internal message buffer locks. the following sequence must be executed by th e application to put the protocol into the poc:default config state. 1. repeat sending the prot ocol command freeze via protocol operation control register (pocr) , until the freeze bit frz in protocol status register 1 (psr1) is set. 2. repeat sending the protocol command default_config via protocol operation control register (pocr) , until the freeze bit frz bit in protocol status register 1 (psr1) is clear and the protstate field in protocol status register 0 (psr0) is set to default_config. table 3-111. protocol control command priorities protocol command priority interrupted by cleared and terminated by reset (highest) 1 none freeze 2 reset ready 3 reset config_complete 3 reset all_slots 4 reset, freeze, ready, config_complet, fatal protocol error reset, freeze, ready, config_complete, fatal protocol error allow_coldstart 5 reset run 6 reset, freeze, fatal protocol error wakeup 7 reset, freeze, fatal protocol error default_config 8 reset, freeze, fatal protocol error config 9 reset halt (lowest) 10 reset, freeze, ready, config_complete, fatal protocol error mfr4300 data sheet, rev. 3 freescale semiconductor 205 chapter 4 port integration module (pim) 4.1 introduction 4.1.1 overview the port integration module implements the interfac es between the flexray ip block, the peripheral modules, and the i/o pins. 4.1.2 features the port integration module incl udes these distinctive features: ? pad control for all functional pads including: ? drive strength enable (dse ), via a control register ? pull enable (pue), via a control register ? pull select (pus), via a control register ? pin multiplexing and direction control for reset mode 4.1.3 modes of operation the port integration module can be put into the following modes: ? functional mode in this mode, the module drives e ach associated pin and has comple te control of th e direction of that pin. the drive strength and pul lup/pulldown enable are controlled via a set of co ntrol registers. ? reset mode in this mode, the pin configuration is changed for: ? clock output control: clk_s0 and clk_s1 ? host interface control: if_sel0 and if_sel1 the control signals become available on the corresponding pins in re set mode. refer to chapter 6, ?clocks and reset generator (crg) ? for reset mode details. this is a high level description on ly; detailed descriptions of opera ting modes are contained in later sections. 4.2 external signal description for detailed descriptions of partic ular pins and signals, refer to section 2.4, ?signal descriptions ?. port integration module (pim) mfr4300 data sheet, rev. 3 206 freescale semiconductor 4.2.1 functional mode table 4-1. pin functions (functional mode) name function direction special configuration 1 host interface a[6:1]/xaddr[14:19] ami address bus / hcs12 expanded address lines. a1-lsb of the ami address bus, xaddr14-lsb of the hcs12 expanded address lines input pu/pd a[7:9] ami address bus input pu/pd oe#/acs0 ami read output enable signal / hcs12 address select input input pu/pd a[12:11]/acs[2:1] ami address bus / hcs12 address select inputs input pu/pd bsel[1:0]#/dbg[0:1] ami byte select / debug strobe point input/output dc/pu/pd d[15:8]/pb[0:7] ami data bus / hcs 12 multiplexed address/data bus. d15 is the msb of the ami data bus, pb0 is the lsb of the hcs12 address/data bus input/output dc/pu/pd d[7:0]/pa[0:7] ami data bus / hcs12 multiplexed address/data bus. d0 is the lsb of the ami data bus, pa7 is the msb of the hcs12 address/data bus input/output dc/pu/pd ce#/lstrb ami chip select signal / hcs 12 low-byte strobe signal input pu/pd we#/rw_cc# ami write enable signal/ hcs 12 read/write select signal input pu/pd a10/eclk_cc ami address bus/ hcs12 cl ock inputhcs12 interface, clock input input pu/pd physical layer interface rxd_bg[2:1] phy data receiver input input pu/pd txen[2:1]# transmit enable for phy output dc txd_bg[1:2]/if_sel[1 :0] phy data transmitter output / ho st interface select input/output dc clock interface chiclk_cc external chi clock input selectable input - clkout controller clock output selectable between disabled, 4/10/40 mhz output dc other reset# hardware reset input input - int_cc# controller interrupt output output dc/od test factory test mode select ? must be tied to logic low in application input pd mfr4300 data sheet, rev. 3 freescale semiconductor 207 4.2.2 reset mode this pin configuration is enable d in reset mode only. refer to chapter 6, ?clocks and reset generator (crg) ? for reset mode details. when the device is in reset mode, the corresponding pads go into input mode with pulldown enabled. 4.3 pim memory map and registers this section provides a detailed description of all registers in the port integration module. only 16-bit reads and 8-bit and 16-bit writes are allowed to all registers. dbg[3:2]/clk_s[1:0] debug strobe point / external chi clock input select output dc oscillator extal/cc_clk crystal driver / external clock input - xtal crystal driver input - 1 acronyms: pc ? (pullup/pulldown controlled) register controlled internal weak pullup/pulldown for a pin in the input mode pd ? (pulldown) internal weak pulldown for a pin in the input mode dc ? (drive strength controlled) register controlled drive strength for a pin in the output mode table 4-2. pin functions (reset mode) name direction speci al configuration 1 1 acronyms: pd ? (pulldown) internal weak pulldown for a pin in the input mode txd_bg[1:2]/if_sel[1:0] input pd dbg[3:2]/clk_s[1:0] input pd table 4-3. port integration module memory map address use access 0x00f0 part id register (pidr) r 0x00f2 asic version number register (avnr) r 0x00f4 host interface pins drive strength register (hipdsr) r/w 0x00f6 physical layer pins drive strength register (plpdsr) r/w 0x00f8 host interface pins pullup/pull down enable register (hipper) r/w 0x00fa host interface pins pullup/pulldown control register (hippcr) r/w 0x00fc physical layer pins pullup/pulldown enable register (plpper) r/w 0x00fe physical layer pins pullup/pulldown control register (plppcr) r/w table 4-1. pin functions (functional mode) (continued) name function direction special configuration 1 port integration module (pim) mfr4300 data sheet, rev. 3 208 freescale semiconductor 4.3.1 port integration module registers 4.3.1.1 part id register (pidr) this register provides the part id (?4300?) in binary coded decimal. 4.3.1.2 asic version number register (avnr) this register provides the asic versi on number (?0000?) in binary coded decimal. 4.3.1.3 host interface pins drive strength register (hipdsr) this register controls the drive strength of the host interface, interrupt, debug, and output clock pins. address in mfr4300 = 0x00f0 1514131211109876543210 r0100001100000000 w reset0100001100000000 figure 4-1. part id register (pidr) address in mfr4300 = 0x00f2 1514131211109876543210 r0000000000000000 w reset0000000000000000 figure 4-2. asic version number register (avnr) address in mfr4300 = 0x00f4 write: any time 1514131211109876543210 r000000000000 clko ut dbg[ 3:2] int_ cc# d[0:1 5]/ pa [ 0 : 7]/pb[ 0:7] w reset0000000000001111 figure 4-3. host interface pins drive strength register (hipdsr) table 4-4. hipdsr field descriptions field description 0 d[0:15]/ pa[0:7]/ pb[0:7] host interface output data drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full 1 int_cc# interrupt output drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full mfr4300 data sheet, rev. 3 freescale semiconductor 209 4.3.1.4 physical layer pins drive strength register (plpdsr) this register controls the drive stre ngth of the flexray physical layer pins. 4.3.1.5 host interface pins pullup/ pulldown enable register (hipper) 2 dbg[3:2] debug output (bits 3 and 2 only) drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full 3 clkout output clock drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full address in mfr4300 = 0x00f6 write: any time 1514131211109876543210 r000000000000 txd_ bg2 txd_ bg1 txen 2# txen 1# w reset0000000000001111 figure 4-4. physical layer pins drive strength register (plpdsr) table 4-5. plpdsr field descriptions field description 0 txen1# transmit enable (channel a) ou tput drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full 1 txen2# transmit enable (channel b) ou tput drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full 2 txd_bg1 transmit data (channel a) output drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full 3 txd_bg2 transmit data (channel b) output drive strength control 0 pin drive strength is reduced to 1/3 of full strength 1 pin drive strength is full address in mfr4300 = 0x00f8 write: any time 1514131211109876543210 r0 0 we#/ rw_ cc# ce#/l strb d[0:1 5]/ pa [ 0 : 7]/pb[ 0:7] a12/a cs2 a11/a cs1 oe#/ acs0 bsel[ 1:0]# a[10: 7] a6/ xadd r14 a5/ xadd r15 a4/ xadd r16 a3/ xadd r17 a2/ xadd r18 a1/ xadd r19 w reset0000000000000000 figure 4-5. host interface pins pull up/pulldown enable register (hipper) table 4-4. hipdsr field descriptions (continued) field description port integration module (pim) mfr4300 data sheet, rev. 3 210 freescale semiconductor this register enables/disables the pull ups/pulldowns of the host interface pins. table 4-6. hipper field descriptions field description 0 a1/ xaddr19 ami address bit 1 / hcs12 expanded address bit 19 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 1 a2/ xaddr18 ami address bit 2 / hcs12 expanded address bit 18 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 2 a3/ xaddr17 ami address bit 3 / hcs12 expanded address bit 17 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 3 a4/ xaddr16 ami address bit 4 / hcs12 expanded address bit 16 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 4 a5/ xaddr15 ami address bit 5 / hcs12 expanded address bit 15 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 5 a6/ xaddr14 ami address bit 6 / hcs12 expanded address bit 14 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 6 a[10:7] ami address bits 7 through 10 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled note the pullup/pulldown for input a10/eclk_cc is enabled only when the ami interface is selected. 7 bsel[1:0]# ami byte select pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 8 oe#/ acs0 ami output enable / hcs12 address select bit 0 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 9 a11/ acs1 ami address bit 11 / hcs12 address select bit 1 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 10 a12/ acs2 ami address bit 12 / hcs12 address select bit 2 pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 11 d[0:15]/ pa[0:7]/ pb[0:7] host interface input data pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled mfr4300 data sheet, rev. 3 freescale semiconductor 211 4.3.1.6 host interface pins pullup/ pulldown control register (hippcr) this register enables/disables the pull ups/pulldowns of the host interface pins. 12 ce#/lstrb ami chip enable / hcs12 low-byte strobe pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 13 we#/rw_c c# ami write enable / hcs12 read/write select pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled address in mfr4300 = 0x00fa write: any time 1514131211109876543210 r0 0 we#/ rw_ cc# ce#/l strb d[0:1 5]/ pa [ 0 : 7]/pb[ 0:7] a12/a cs2 a11/a cs1 oe#/ acs0 bsel[ 1:0]# a[10: 7] a6/ xadd r14 a5/ xadd r15 a4/ xadd r16 a3/ xadd r17 a2/ xadd r18 a1/ xadd r19 w reset0000000000000000 figure 4-6. host interface pins pull up/pulldown control register (hippcr) table 4-7. hippcr field descriptions field description 0 a1/ xaddr19 ami address bit 1 / hcs12 expanded address bit 19 pullup/pulldown control 0 pulldown 1 pullup 1 a2/ xaddr18 ami address bit 2 / hcs12 expanded address bit 18 pullup/pulldown control 0 pulldown 1 pullup 2 a3/ xaddr17 ami address bit 3 / hcs12 expanded address bit 17 pullup/pulldown control 0 pulldown 1 pullup 3 a4/ xaddr16 ami address bit 4 / hcs12 expanded address bit 16 pullup/pulldown control 0 pulldown 1 pullup 4 a5/ xaddr15 ami address bit 5 / hcs12 expanded address bit 15 pullup/pulldown control 0 pulldown 1 pullup 5 a6/ xaddr14 ami address bit 6 / hcs12 expanded address bit 14 pullup/pulldown control 0 pulldown 1 pullup 6 a[10:7] ami address bits 7 through 10 pullup/pulldown control 0 pulldown 1 pullup table 4-6. hipper field descriptions (continued) field description port integration module (pim) mfr4300 data sheet, rev. 3 212 freescale semiconductor 4.3.1.7 physical layer pins pullup/pulldown enable register (plpper) this register enables/disables the pullups/ pulldowns of the flexray physical layer pins. 7 bsel[1:0]# ami byte select pullup/pulldown control 0 pulldown 1 pullup 8 oe#/acs0 ami output enable / hcs12 address select bit 0 pullup/pulldown control 0 pulldown 1 pullup 9 a11/acs1 ami address bit 11 / hcs12 address select bit 1 pullup/pulldown control 0 pulldown 1 pullup 10 a12/acs2 ami address bit 12 / hcs12 address select bit 2 pullup/pulldown control 0 pulldown 1 pullup 11 d[0:15]/ pa[0:7]/pb[0: 7] host interface input data pullup/pulldown control 0 pulldown 1 pullup 12 ce#/lstrb ami chip enable / hcs12 low-byte strobe pullup/pulldown control 0 pulldown 1 pullup 13 we#/rw_c c# ami write enable / hcs12 read/write select pullup/pulldown control 0 pulldown 1 pullup address in mfr4300 = 0x00fc write: any time 1514131211109876543210 r00000000000000 rxd_ bg2 rxd_ bg1 w reset0000000000000000 figure 4-7. physical layer pins pull up/pulldown enable register (plpper) table 4-8. plpper field descriptions field description 0 rxd_bg1 receive data (channel a) pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled 1 rxd_bg2 receive data (channel b) pullup/pulldown enable 0 pullup/pulldown disabled 1 pullup/pulldown enabled table 4-7. hippcr field d escriptions (continued) field description mfr4300 data sheet, rev. 3 freescale semiconductor 213 4.3.1.8 physical layer pins pullup/ pulldown control register (plppcr) this register enables/disables the pull ups/pulldowns of the host interface pins. 4.4 functional description the port integration module provi des the capability to configure al l functional i/o pins regarding: ? output drive with two selectable drive strengths ? pullup or pulldown ? pin multiplexing and pin configur ation constraints for reset mode 4.4.1 functional mode in functional mode, the port integration module controls the functional interface: ? host interface ? physical layer interface ? clock interface the module provides pullup/pulldown and drive strength control through configuration registers via the ipbus interface. the actual control registers are described in section 4.3, ?pim memory map and registers ?. 4.4.2 reset mode see section 4.2.2, ?reset mode ? and chapter 6, ?clocks and reset generator (crg) ? for reset mode details. address in mfr4300 = 0x00fe write: any time 1514131211109876543210 r00000000000000 rxd_ bg2 rxd_ bg1 w reset0000000000000000 figure 4-8. physical layer pins pullup/pulldown control register (plppcr) table 4-9. plppcr field descriptions field description 0 rxd_bg1 receive data (channel a) pullup/pulldown control 0 pulldown 1 pullup 1 rxd_bg2 receive data (channel b) pullup/pulldown control 0 pulldown 1 pullup port integration module (pim) mfr4300 data sheet, rev. 3 214 freescale semiconductor mfr4300 data sheet, rev. 3 freescale semiconductor 215 chapter 5 dual output voltage regulator (vreg3v3v2) 5.1 introduction the vreg3v3v2 is a dual output voltage regulator providing two separate 2.5 v (typical) supplies differing in the amount of current th at can be sourced. the regulator i nput voltage range is from 3.3 v up to 5 v (typical). 5.1.1 features the block vreg3v3v2 includes these distinctive features: ? two parallel, linear voltage regulators ? bandgap reference ? power-on reset (por) ? low-voltage reset (lvr) 5.1.2 modes of operation vreg3v3v2 can operate in two modes on mfr4300: ? full-performance mode (fpm) the regulator is active, providing the nominal supply voltage of 2.5 v with full current sourcing capability at both outputs. feat ures lvr (low-voltage reset) and por (power-on reset) are available. ? shutdown mode controlled by v ddr . this mode is characterized by minimum power consumption. the regulator outputs are in a high impedance state; only the por feature is available, and lvr is disabled. this mode must be used to di sable the chip intern al regulator vreg3v3v2, i.e., to bypass the vreg3v3v2 to use external supplies. 5.1.3 block diagram figure 5-1 shows the function principle of vreg3v3v2 by means of a block diagram. the regulator core reg consists of two parallel sub- blocks, reg1 and reg2, providing two independent output voltages. dual output voltage regulator (vreg3v3v2) mfr4300 data sheet, rev. 3 216 freescale semiconductor figure 5-1. vreg3v3 block diagram lv r por v ddr v dd por lvr ctrl v ss v ddosc v ssosc reg reg2 reg1 pin v dda v ssa reg: regulator core ctrl: regulator control lvr: low voltage reset por: power-on reset v ssr dual output voltage regulator (vreg3v3v2) mfr4300 data sheet, rev. 3 freescale semiconductor 217 5.2 external signal description due to the nature of vreg3v3v2 being a voltage regulator providing the chip internal power supply voltages most signals are power s upply signals connected to pads. table 5-1 shows all signals of vreg3v 3v2 associated with pins. note check device overview chapter for connectivity of the signals. 5.2.1 v ddr , v ssr ? regulator power input signal v ddr is the power input of vreg3v3v2. all curren ts sourced into the regulator loads flow through this pin. a chip extern al decoupling capacitor (100 nf ? 220 nf, x7r ceramic) between v ddr and v ssr can smoothen ripple on v ddr . for entering shutdown mode, pin v ddr must be tied to ground. in that case, v dd /v ss and v ddosc /v ssosc must be provided externally. 5.2.2 v dda , v ssa ? regulator reference supply signals v dda /v ssa which are supposed to be relatively quiet are used to supply the analog parts of the regulator. internal precisi on reference circuits are supplied from th ese signals. a chip external decoupling capacitor (100 nf ? 220 nf, x7r ceramic) between v dda and v ssa can further improve the quality of this supply. table 5-1. vreg3v3v2 ? signal properties name port function reset state pullup v ddr ? vreg3v3v2 power input (positive supply) ? ? v ssr ? vreg3v3v2 power input (ground) ? ? v dda ? vreg3v3v2 quiet input (positive supply) ? ? v ssa ? vreg3v3v2 quiet input (ground) ? ? v dd ? vreg3v3v2 primary output (positive supply) ? ? v ss ? vreg3v3v2 primary output (ground) ? ? v ddosc ? vreg3v3v2 secondary output (positive supply) ? ? v ssosc ? vreg3v3v2 secondary output (ground) ? ? dual output voltage regulator (vreg3v3v2) mfr4300 data sheet, rev. 3 218 freescale semiconductor 5.2.3 v dd , v ss ? regulator output1 (core logic) signals v dd /v ss are the primary outputs of vreg3v3v2 that provide the power supply for the core logic. these signals are connected to device pins to allow exte rnal decoupling capacitors (100 nf ? 220 nf, x7r ceramic). in shutdown mode an external supply at v dd /v ss can replace the voltage regulator. 5.2.4 v ddosc , v ssosc ? regulator output2 (osc) signals v ddosc /v ssosc are the secondary outputs of vreg3v3v2 that provide the power supply for the oscillator. these signals are connect ed to device pins to allow extern al decoupling capacitors (100 nf ? 220 nf, x7r ceramic). in shutdown mode an external supply at v ddosc /v ssosc can replace the voltage regulator. 5.3 functional description block vreg3v3v2 is a voltage regulator as depicted in figure 5-1 . the regulator func tional elements are the regulator core (reg), a power -on reset module (por) and a low-vol tage reset module (lvr). there is also the regulator control block (ctrl) which manages the operating modes of vreg3v3v2. 5.3.1 reg ? regulator core vreg3v3v2, respectively its regulator core has two parallel, i ndependent regulation loops (reg1 and reg2) that differ only in the amount of current that can be sourced to the connected loads. therefore, only reg1 providing the supply at v dd /v ss is explained. the principle is also valid for reg2. the regulator is a linear series regulator with a bandgap reference in its fu ll-performance mode and a voltage clamp in reduced-power mode. a ll load currents flow from input v ddr to v ss or v ssosc , the reference circuits are connected to v dda and v ssa . 5.3.2 full-performance mode in full-performance mode, a fra ction of the output voltage (v dd ) and the bandgap reference voltage are fed to an operational amplifier. the amplified input voltage di fference controls the gate of an output driver. 5.3.3 por ? power on reset this functional block monitors output v dd . if v dd is below v pord , signal por is high; if it exceeds v pord , the signal goes low. the transition to low forces the cpu into the power-on sequence. due to its role during chip power -up, this module must be active in all operating modes of vreg3v3v2. dual output voltage regulator (vreg3v3v2) mfr4300 data sheet, rev. 3 freescale semiconductor 219 5.3.4 lvr ? low voltage reset block lvr monitors the primary output voltage v dd . if it drops below the assertion level (v lvra ) signal lvr asserts and when rising above the deassertion level (v lvrd ) signal lvr deasserts again. the lvr function is available only in full-performance mode. 5.3.5 ctrl ? regulator control this part contains digital functionality needed to control the operating modes. 5.4 resets this subsection describes how vreg3v3v2 controls the re set of the cc. the reset values of registers and signals are provided in section 3.3, ?memory map and register description? . possible reset sources are listed in table 5-2 . 5.4.1 power on reset during chip power-up the digital core ma y not work if its supply voltage v dd is below the por deassertion level (v pord ). therefore, signal por, which forces the other blocks of the device into reset, is kept high until v dd exceeds v pord . then por becomes low and the reset generator of the device continues the start-up sequence. 5.4.2 low voltage reset for information on low-voltage reset see section 5.3.4, ?lvr ? low voltage reset? . table 5-2. vreg3v3v2 ? reset sources reset source local enable power-on reset always active low-voltage reset always active dual output voltage regulator (vreg3v3v2) mfr4300 data sheet, rev. 3 220 freescale semiconductor mfr4300 data sheet, rev. 3 freescale semiconductor 221 chapter 6 clocks and reset generator (crg) 6.1 introduction 6.1.1 overview this document describes the crg operation in functi onal mode and only those aspects of it which are useful users. additional topics as system clock generation or functiona lity while the crg is in another operational modes are out of th e scope of this documentation. 6.1.2 features the crg includes the following main features: ? system reset generation from pow er-on and external reset events ? system reset generation from low voltage reset event ? controllable system reset ge neration under low quality clock situations (clock monitor) ? system reset indication ? host interface selection ? control signals selection for clkout clock output ? system clocks generation clocks and reset generator (crg) mfr4300 data sheet, rev. 3 222 freescale semiconductor 6.2 mfr4300 relevant pins for the crg table 6-1 describes the mfr4300 pins relevant for the crg block. 6.3 crg registers 6.3.1 detection enable register (der) table 6-1. mfr4300 relevant pins for the crg pin name 1 1 # ? signal is active-low in/out pin type 2,3 2 acronyms: pc ? (pullup/pulldown controlled) register controlled internal weak pullup/pulldown for a pin in the input mode pd ? (pulldown) internal weak pulldown for a pin in the input mode dc ? (drive strength controlled) register controll ed drive strength for a pin in the output mode z ? tristated pin 3 reset state: all pins with the pc option ? pullup/pulldown is disabled, all pins with the dc option ? have full drive strength functional description txd_bg[1:2]/if_sel[1:0] i/o dc/pd phy data transmitter output / host interface select chiclk_cc i - external chi clock input ? selectable clkout/tm0 i/o dc controller clock output?selec table between disabled, 4/10/40 mhz/ test mode selection for production testing only reset# i - hardware reset input int_cc# o od/dc controller interrupt output test i pd factory test mode select? should be tied to logic low in application dbg[3:2]/clk_s[1:0] i/o dc/pd debug strobe point / output clock select extal/clk_cc i - crystal driver / external clock pin xtal i - crystal driver pin address in mfr4300 = 0x00e0 write: any time 1514131211109876543210 r000000000000000 cmie w reset0000000000000000 figure 6-1. detection enable register (der) table 6-2. der field descriptions field description 0 cmie clock monitor mechanism enable 0 range filter disabled 1 range filter enabled clocks and reset generator (crg) mfr4300 data sheet, rev. 3 freescale semiconductor 223 note after reset, the clock moni tor mechanism is disabled. 6.3.2 clock and reset status register (crsr) note on a power-on or low-volta ge reset, cmif and prif are both cleared to ?0?. 6.4 functional description 6.4.1 reset generation the crg will provide a system reset in any of th e following events: power-on, low-voltage or clock monitor failure detected, lo w level detected at the reset# pin. entry into reset is asynchronous and does not require a clock. however, the mfr4300 cannot seque nce out of reset in functional mode without a system clock. table 6-4 depicts reset sources priorities. the crg scans, during different peri ods depending on the origin of the reset source, the interface type, the ami clock source and the clkout mode selection pins: if_sel[1:0] and clk_s[1:0]. address in mfr4300 = 0x00e2 write: any time 1514131211109876543210 r00000 cdcv ecs 0 0 0 0 erif prif cmif lvif w reset0000000000000000 figure 6-2. clock and reset status register (crsr) table 6-3. crsr field descriptions field description 0 lv i f low voltage reset interrupt flag ? set when a low-voltage reset has occurred. cleared when writing a 1. writing 0 has no effect. 1 cmif clock monitor reset interrupt flag ? set when a clock-monitor reset has occurred. cleared when writing a 1. writing 0 has no effect. note: if lvif bit or prif bit is set to 1 then the cmif bit value is 0. 2 prif power-on reset interrupt flag ? set when a power-on reset has occurred. cleared when writing a 1. writing 0 has no effect. 3 erif external reset interrup t flag ? set when a external reset has occurred. cleared when writing a 1. writing 0 has no effect. note: if lvif bit or prif bit is set to 1 then the erif bit value is ?0?. 8 ecs chi and host interface clock source 0 chi and host interface are clocked by extal/clk_cc 1 chi and host interface are clocked by chiclk_cc 10-9 cdcv clkout division control value ? contains sampled value of clk_s[1:0]. the crg writes this value after a power-on, low-voltage or clock monitor reset, accord ing to the values sampled on the clk_s[1:0] pins. see ta b l e 2 - 5 for coding. clocks and reset generator (crg) mfr4300 data sheet, rev. 3 224 freescale semiconductor note once the crg had started a reset proce dure it will not abandon it unless a reset event with more priority was de tected. the reset pr ocedure which has the same priority, as currently running one, stops the previo us procedure and gets executed. 6.4.1.1 power-on reset when the power-on reset signal is asserted the crg asse rts the system reset signal . the crg will deassert synchronously the system reset signal approximately 16420 extal/clk_cc clock periods after the deassertion of the power-on reset signal. the crg asserts the int_cc# interrupt line and the powe r-on reset interrupt flag, crsr . prif , on the rising edge of the power-on reset signal. note the crg deasserts the int_cc# signal when crsr.prif, crsr.lvif, crsr.cmif and crsr.erif bits are ?0?. figure 6-3 illustrates the power-on reset situation. table 6-4. crg reset sources priorities reset source block to reset priority power-on reset whole device high low voltage or clock monitor failure (if enabled) reset whole device external reset whole device low clocks and reset generator (crg) mfr4300 data sheet, rev. 3 freescale semiconductor 225 figure 6-3. crg power on reset 6.4.1.2 low voltage and clock monitor reset when the low voltage reset or clock monitor failure signal is asserted the crg asserts the system reset signal. the crg will deassert synchronously the system reset si gnal approximately 16420 extal/clk_cc clock periods after the dea ssertion of the low voltage re set or clock monitor failure signal. the crg asserts the int_cc# interrupt line and the low volta ge reset interrupt flag, crsr.lvif , on the rising edge of the low voltage re set signal. the crg asserts the int_cc# interrupt line and the clock monitor failure interrupt flag, crsr.cmif , on the rising edge of the clock monitor failure signal. note the crg deasserts the int_cc# signal when crsr.prif, crsr.lvif, crsr.cmif and crsr.erif bits are ?0?. figure 6-4 and figure 6-5 show the operations performed by the cr g when a low voltage reset or a clock monitor failure signal occur. vdd power-on reset system reset ~16420 extal/clk_cc periods crsr.prif int_cc# clocks and reset generator (crg) mfr4300 data sheet, rev. 3 226 freescale semiconductor figure 6-4. low voltage reset figure 6-5. clock monitor failure reset 6.4.1.3 external reset when the reset# signal is asserted the crg asserts the syst em reset signal. the crg will deassert the system reset signa l approximately 70 extal/clk_cc clock periods after th e deassertion of the reset# . the crg asserts the int_cc# interrupt line and the external reset interrupt flag, crsr.erif, on the assertion of the reset# signal. note the crg deasserts the int_cc# signal when crsr.prif, crsr.lvif, crsr.cmif and crsr.erif bits are ?0?. figure 6-6 illustrates an external reset scheme. low voltage reset system reset ~16420 extal/clk_cc periods crsr.lvif int_cc# clock monitor failure system reset ~16420 extal/clk_cc periods crsr.cmif (if enabled) int_cc# clocks and reset generator (crg) mfr4300 data sheet, rev. 3 freescale semiconductor 227 figure 6-6. external reset 6.4.2 interface selection the interface mode select ion is done when the txd_bg[1:2]/if_sel[1:0] pins are in the if_sel[1:0] mode. in the txd_bg[1:2] modes the pads are outputs from the mfr4300 device. note the pim block selects the txd_bg[1 :2]/if_sel[1:0] pads modes based on the system reset signal. 6.4.2.1 interface and ami clock selection the interface selection is made upon the levels on the bus signal if_sel[1:0] while a power-on, low voltage, clock monitor or external reset process is ongoing. the crg latches the if_sel[1:0] during the latching window as presented on figure 6-7 and figure 6-8 . figure 6-7. interface selection during power-on or low voltage reset or clock monitor failure system reset ~70 extal/clk_cc periods crsr.erif int_cc# reset# power-on reset or if_sel[1:0] low voltage reset or clock monitor failure ~16380 extal/clk_cc periods ~16410 extal/clk_cc periods latching window clocks and reset generator (crg) mfr4300 data sheet, rev. 3 228 freescale semiconductor figure 6-8. interface selection during external reset next table shows the interface selecti on encoding provided by the crsr.ecs bit: if, after the evaluation, the if_sel[1:0] are both high, the crg sets to 1 the crsr . ecs bit; otherwise the crg resets that bit. 6.4.3 clkout mode selection and control the clkout mode selection is done when the dbg[3:2]/clk_s[1:0] pins are in the clk_s[1:0] mode. in the dbg[3:2] modes the pads are outputs from the mfr4300 device. note the pim block selects the dbg[3:2]/c lk_s[1:0] pads modes based on the system reset signal. the clkout mode selection is made upon the levels of the clk_s[1:0] signals in the latching window while a power-on, low voltage, clock monitor or exte rnal reset process is ongoing. the crg latches the clk_s[1:0] signal values during the latching window as presented on figure 6-9 , figure 6-10 and figure 6-11 . the latched values are indicated in the crsr.cdcv field. table 6-5. if_sel[1:0] encoding by crsr.ecs if_sel1 if_sel0 crsr.ecs 100 010 111 reset# if_sel[0;1] ~30 extal/clk_cc periods ~60 extal/clk_cc periods latching window clocks and reset generator (crg) mfr4300 data sheet, rev. 3 freescale semiconductor 229 figure 6-9. clkout mode selection and control du ring low-voltage reset or clock monitor failure clk_s[1:0] low voltage reset or clock monitor failure ~16380 extal/clk_cc periods ~16410 extal/clk_cc periods latching window system reset ~16420 extal/clk_cc periods clkout clocks and reset generator (crg) mfr4300 data sheet, rev. 3 230 freescale semiconductor figure 6-10. clkout mode selection and control during external reset clk_s[1:0] ~30 extal/clk_cc periods ~60 extal/clk_cc periods latching window system reset ~70 extal/clk_cc periods clkout reset# clocks and reset generator (crg) mfr4300 data sheet, rev. 3 freescale semiconductor 231 figure 6-11. clkout mode selection and control during power-on reset clk_s[1:0] power-on reset ~16380 extal/clk_cc periods ~16410 extal/clk_cc periods latching window system reset ~16420 extal/clk_cc periods clkout clocks and reset generator (crg) mfr4300 data sheet, rev. 3 232 freescale semiconductor mfr4300 data sheet, rev. 3 freescale semiconductor 233 chapter 7 oscillator (flexray) 7.1 introduction the flexray module provides one oscillator concept: ? a robust full swing pierce oscillator with the po ssibility to feed in an external square wave 7.1.1 features the pierce oscillator provi des the following features: ? wide high frequency operation range ? no dc voltage applied across the crystal ? full rail-to-rail (2.5 v nom inal) swing oscillation wi th low em susceptibility ? fast start up common features: ? clock monitor (cm) ? operation from the v ddosc 2.5 v (nominal) supply rail 7.1.2 modes of operation one mode of operation exists: ? full swing pierce oscillator mode that can also be used to feed in an externally generated square wave suitable for high frequenc y operation and harsh environments 7.2 external signal description this section lists and describes th e signals that connect off chip. 7.2.1 v ddosc and v ssosc ? osc operating voltage, osc ground these pins provide the operating voltage (v ddosc ) and ground (v ssosc ) for the flexray circuitry. this allows the supply voltage to th e flexray to be independently bypassed. 7.2.2 extal and xtal ? cl ock/crystal source pins these pins provide the interface for either a crystal or a cmos compatib le clock to control the internal clock generator circuitry. exta l is the external cl ock input or the input to the crystal osc illator amplifier. oscillator (flexray) mfr4300 data sheet, rev. 3 234 freescale semiconductor xtal is the output of the crystal os cillator amplifier. all internal sy stem clocks are derived from the extal input frequency. note freescale semiconductor recommends an evaluation of the application board and chosen resonator or crysta l by the resonator or crystal supplier . the crystal circuit is changed from standard. the pierce circuit is not su ited for overtone resonato rs and crystals without a careful component selection. for more information, see the extal pin description in chapter 2. oscillator (flexray) mfr4300 data sheet, rev. 3 freescale semiconductor 235 7.3 memory map and register definition the crg contains the registers a nd associated bits for controlli ng and monitoring the flexray module. 7.4 functional description the flexray block has two external pins, extal and xtal. the oscillator input pin, extal, is intended to be connected to either a crystal or an external clock source . the xtal pin is an output signal that provides crysta l circuit feedback. a buffered extal signal, oscclk, becomes the intern al reference clock. to improve noise immunity, the oscillator is powered by the v ddosc and v ssosc power supply pins. 7.4.1 clock monitor (cm) the clock monitor circuit is based on an internal resistor-capacitor (rc) time delay so that it can operate without a clock. if no oscclk edges are detected within this rc time delay, th e clock monitor indicates a failure which asserts self clock m ode or generates a system reset depe nding on the state of the scme bit. if the clock monitor is disabled or the presence of clocks is detecte d, no failure is indicated. the clock monitor function is enabled/disabled by the cme control bit, described in chapter 6, ?clocks and reset generator (crg) ?. 7.5 resets flexray contains a clock moni tor, which can trigger a reset. the cont rol bits and status bits for the clock monitor are described in chapter 6, ?clocks and reset generator (crg) ?. oscillator (flexray) mfr4300 data sheet, rev. 3 236 freescale semiconductor mfr4300 data sheet, rev. 3 freescale semiconductor 237 appendix a electrical characteristics a.1 general note the electrical characteristics given in this appendix are preliminary and must be used as a guid e only. values cannot be guaranteed by freescale and are subject to change without notice. note the part is specified and tested over the 5 v and 3.3 v ranges. for the intermediate range, generally the el ectrical specifications for the 3.3 v range apply, but the part is not tested in production test in the intermediate range. this appendix provides the most a ccurate electrical information for the mfr4300 device available at the time of publication. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. the following classifications are used and the parameters are ta gged accordingly in the column labeled ?c? in the parameter tables, where appropriate. p: parameters that are guaranteed during production testing on each individual device. c: parameters that are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t: parameters that are achieved by design charact erization on a small samp le size from typical devices under typical condi tions unless otherwise noted. all valu es shown in the typical column are within this category. d: parameters that are derived mainly from simulations. electrical characteristics mfr4300 data sheet, rev. 3 238 freescale semiconductor a.1.2 power supply the mfr4300 uses several pins to supply power to the i/o pins, os cillator and the digital core. the vdda, vssa pair supplies th e internal voltage regulator. the vddx, vssx, vddr and vssr pairs supply the i/o pins, vddr supplies also the internal voltage regulator. vdd2_5 and vss2_5 are the supply pins for the digital logic, vddosc , vssosc supply the oscillator. vdda, vddx, vddr as well as vssa, vssx, vssr are connected by anti-parallel diodes for esd protection. note in the following context, vdd5 is used for either vdda, vddr and vddx; vss5 is used for either vs sa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the curren ts flowing into the vdda, vddx and vddr pins. vdd is used for vdd2_5 and vddos c, vss is used for vss2_5 and vssosc. idd is used for the current flowing into vdd2_5. a.1.3 pins there are four groups of functional pins. a.1.3.1 3.3v i/o pins those i/o pins have a nominal level of 3.3v. this cla ss of pins is comprised of all i/o pins (all mfr4300 pins excluding extal, xtal and all power supply pins ).the internal structure of all those pins is identical, however some of the func tionality may be disabled. e.g. fo r the input-only pins the output drivers are disabled permanently. a.1.3.2 oscillator the pins extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddosc. a.1.3.3 vddr this pin is used to enable the on chip voltage regulator. electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 239 a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could result in extern al power supply going out of regulation. ensure external v dd5 load will shunt current greater than maxi mum injection current. this will be the greatest risk when the cc is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings caution long-term exposure to absolute ma ximum ratings may affect device reliability, and permanent damage may occur if operate exceeding the rating. the device should be opera ted under recommended operating condition. absolute maximum ratings are stre ss ratings only. a functional operatio n under or outside those maxima is not guaranteed. stre ss beyond those limits may affe ct the reliability or caus e permanent damage of the device. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). table a-1. absolute maximum ratings num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 ?0.3 6.5 v 2 digital logic supply voltage 1 v dd ?0.3 3.0 v 3 oscillator supply voltage 1 v ddosc ?0.3 3.0 v 4 voltage difference vddx to vddr and vdda vddx ?0.3 0.3 v 5 voltage difference vssx to vssr and vssa vssx ?0.3 0.3 v 6 digital i/o input voltage 2 v in ?0.3 6.5 v 7 extal, xtal inputs v ilv ?0.3 3.0 v 8 instantaneous maximum current single pin limit for all digital i/o pins 3 i d ?25 +25 ma 9 instantaneous maximum current single pin limit for extal, xtal 4 i dl ?25 +25 ma 10 operating temperature range (packaged) t a ?40 +125 o c 11 operating temperature range (junction) t j ?40 +150 o c 12 storage temperature range t stg ? 65 +155 c electrical characteristics mfr4300 data sheet, rev. 3 240 freescale semiconductor a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qua lification for automotive grade integrated circuits. during the device qualification esd stresses we re performed for the human body model (hbm), the machine model ( mm) and the charge device model. a device will be defined as a fail ure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametr ic and functional testing is perf ormed per the applicable device specification at room temperature followed by hot te mperature, unless specified otherwise in the device specification. 1 the device contains an internal voltage regulator to ge nerate the logic and osc supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. 2 ac over or undershoots for 2v beyond the supply if limited to 20ns length are allowed. 3 all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . 4 those pins are internally clamped to v ssosc and v ddosc . table a-2. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulse per pin positive negative ?? 3 3 machine series resistance r1 0 storage capacitance c 200 pf number of pulse per pin positive negative ?? 3 3 latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v table a-3. esd and latch-up protection characteristics num c rating symbol min max unit 1 t human body model (hbm) v hbm 2000 ? v 2 t machine model (mm) v mm 200 ? v 3 t charge device model (cdm) v cdm 500 ? v 4 t latch-up current at t a = 125 c positive negative i lat +100 ?100 ? ma 5 t latch-up current at t a = 27 c positive negative i lat +200 ?200 ?ma electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 241 a.1.7 operating conditions this section describes the opera ting conditions of the device. unle ss otherwise noted those conditions apply to all the following data. note refer to the temperature rating of the de vice (c, v, m) with regards to the ambient temperature t a and the junction temperature t j . for power dissipation calcula tions refer to section a.1.8, ?power dissipation and thermal characteristics ?. a.1.8 power dissipation an d thermal characteristics power dissipation and thermal character istics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: eqn. a-1 t j = junction temperature [c] t a = ambient temperature [c] p d = total chip power dissipation [w] ja = package thermal resistance [c/w] the total power dissipation can be calculated from: table a-4. operating conditions rating symbol min typ max unit oscillator and quartz frequency f osc ? 40.000 40.000 mhz quartz overtone fundamental frequency quartz frequency stability at t j f stb ?1500 300 1500 ppm voltage difference vddx to vddr and vdda d vddx ?0.1 0 0.1 v voltage difference vssx to vssr and vssa d vssx ?0.1 0 0.1 v i/o, regulator and analog supply v dd5 2.97 3.3 5.5 v digital logic supply voltage 1 1 the device contains an internal voltage regulator to generate the logic and osc supply out of the i/o supply. v dd 2.25 2.5 2.75 v oscillator supply voltage 1 v ddosc 2.25 2.5 2.75 v operating junction temperature range t j ?40 ? +140 o c operating ambient temperature range 2 2 refer to section a.1.8, ?power dissipation and thermal characteristics ? for more information about the relation between ambient temperature t a and device junction temperature t j . t j ?40 +27 +125 o c t j t a p d ja ? () + = electrical characteristics mfr4300 data sheet, rev. 3 242 freescale semiconductor eqn. a-2 p int = chip internal power dissipation [w] two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled eqn. a-3 eqn. a-4 p io is the sum of all output currents on i/o ports associated with vddx and vddr. for r dson is valid: eqn. a-5 respectively eqn. a-6 2. internal voltage regulator enabled eqn. a-7 i ddr is the current shown in table a-8 and not the overall current flowing into vddr, which additionally contains the current flowing into the external loads with output high. eqn. a-8 p io is the sum of all output currents on i/o ports associated with vddx and vddr. p d p int p io + = p int i dd v dd ? i ddosc v ddosc ? i dda v dda ? ++ = p io r dson i io i 2 ? i = r dson v ol i ol --------- - ; for outputs driven low = r dson v dd5 v oh ? i oh ----------------------------- - ; for outputs driven high = p int i ddr v ddr ? i dda v dda ? + = p io r dson i io i 2 ? i = electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 243 a.1.9 i/o characteristics this section describes the characteri stics of all 3.3v i/o pins. all para meters are not always applicable, e.g. not all pins feature pullup/pulldown resistances. table a-5. thermal package simulation details num rating symbol value unit 1 junction to ambient lqfp64, single sided pcb 1,2 , natural convection 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissi pation of other components on the board, and board thermal resistance. 2 per semi g38-87 and eia/jedec standard 51-2 with the single layer horizontal pc board according to eia/jedec standard 51-3 r ja tbd o c/w 2 junction to ambient lqfp64, double sided pcb with 2 internal planes 1,3 , natural convection 3 per eia/jedec standard 51-6 with the four layer horizontal pc board (double-sided pcb with two internal planes) according to eia/jedec standard 51-7 r jma tbd o c/w 3 junction to ambient lqfp64 (@200 ft/min), single sided pcb 1,3 r jma tbd o c/w 4 junction to ambient lqfp64 (@200 ft/min), double sided pcb with 2 internal planes 1,3 r jma tbd o c/w 5 junction to board lqfp64 4 4 thermal resistance between the die and the printed circuit board per eia/jedec standard 51-8. board temperature is measured on the top surface of the board near the package. r jb tbd o c/w 6 junction to case lqfp64 5 5 thermal resistance between the die and t he case top surface as measured by the cold plate method (mil spec-883 method 1012.1). r jc tbd o c/w 7 junction to package top lqfp64 6 , natural convection 6 thermal characterization parameter indicating the temperatur e difference between package top and the junction temperature per eia/jedec standard 51-2. jt tbd o c/w table a-6. 5v i/o characteristics (v dd5 = 5v) conditions are shown in figure a-4 , unless otherwise noted. num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 ??v t input high voltage v ih ??v dd5 +0.3 v 2 p input low voltage v il ? ? 0.35*v dd5 v t input low voltage v il v ss5 ?0.3 ? ? v 3 c input hysteresis v hys ?250?mv 4 p high impedance (off-state) leakage current v in =v dd or v ss , all input/output and output pins i in ?2.5 ? +2.5 ua 5 p output high voltage (pins in output mode) @50% partial drive i oh = ?2ma v oh v dd5 ?0.8 ? ? v electrical characteristics mfr4300 data sheet, rev. 3 244 freescale semiconductor 6 p output high voltage (pins in output mode) @100% full drive i oh = ?10ma v oh v dd5 ?0.8 ? ? v 7 p output low voltage (pins in output mode) @50% partial drive i ol = +2ma v ol ??0.8v 8 p output low voltage (pins in output mode) @100% full drive i ol = +10ma v ol ??0.8v 9 p internal pullup device current, tested at v il max i pul ? ? ?130 ua 10 p internal pullup device current, tested at v ih min. i puh ?10 ? ? ua 11 p internal pulldown device current, tested at v ih min. i pdh ??130ua 12 p internal pulldown device current, tested at v il max i pdl 10 ? ? ua 13 d input capacitance (input, input/output pins) c in ?7?pf 14 t injection current 1 ma single pin limit i ics ?2.5 ? 2.5 total device limit. sum of all injected currents i icp ?25 ? 25 15 p load capacitance 50% partial drive 100% full drive c l ?? 25 50 pf 1 refer to section a.1.4, ?current injection ?, for more information. table a-7. 3.3v i/o characteristics (v dd5 = 3.3v) conditions are v ddx =3.3v 10% temperature from ?40 o c to +140 o c, unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 ??v t input high voltage v ih ??v dd5 +0.3 v 2 p input low voltage v il ? ? 0.35*v dd5 v t input low voltage v il v ss5 ?0.3 ? ? v 3 c input hysteresis v hys ? 250 ? mv 4 p high impedance (off-sta te) leakage current v in =v dd or v ss , all input/output and output pins i in ?2.5 ? +2.5 ua 5 p output high voltage (pins in output mode) @50% partial drive i oh = ?0.75ma v oh v dd5 ?0.4 ? ? v table a-6. 5v i/o characteristics (v dd5 = 5v) (continued) conditions are shown in figure a-4 , unless otherwise noted. num c rating symbol min typ max unit electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 245 a.1.10 supply currents all measurements are done without out put loads. unless otherwise noted, the currents are measured with internal voltage regulator enabled and a 40 mhz oscillator, in standard pierce mode. production testing is performed using a square wave signal at the extal input. 6 p output high voltage (pins in output mode) @100% full drive i oh = ?4.5ma v oh v dd5 ?0.4 ? ? v 7 p output low voltage (pins in output mode) @50% partial drive i ol = +0.9ma v ol ??0.4v 8 p output low voltage (pins in output mode) @100% full drive i ol = +5.5ma v ol ??0.4v 9 p internal pullup device current, tested at v il max i pul ? ? ?60 ua 10 p internal pullup device current, tested at v ih min. i puh ?6 ? ? ua 11 p internal pulldown device current, tested at v ih min. i pdh ? ? 60 ua 12 p internal pulldown device current, tested at v il max i pdl 6??ua 13 d input capacitance (input, input/output pins) c in ?7?pf 14 t injection current 1 ma single pin limit i ics ?2.5 ? 2.5 total device limit. sum of all injected currents i icp ?25 ? 25 15 p load capacitance 50% partial drive 100% full drive c l ?? 25 50 pf 1 refer to section a.1.4, ?current injection ? for more information. table a-8. supply current characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 p run supply currents internal regulator enabled ?40 ci dd5 ??tbdma 25 c??tbd 140 c??tbd table a-7. 3.3v i/o characteristics (v dd5 = 3.3v) (continued) conditions are v ddx =3.3v 10% temperature from ?40 o c to +140 o c, unless otherwise noted num c rating symbol min typ max unit electrical characteristics mfr4300 data sheet, rev. 3 246 freescale semiconductor a.2 voltage regulator (vreg) a.2.1 operating conditions table a-9. voltage regulator ? operating conditions conditions are shown in ta b l e a - 4 unless otherwise noted num c characteristic symbol min typical max unit 1 p input voltages v vddr,a 2.97 ? 5.5 v 2 p regulator current shutdown mode i reg ?tbd40 a 3 p output voltage core full performance mode shutdown mode v dd 2.45 ? 2.5 ? 1 1 high impedance output 2.75 ? v v 4 p output voltage osc full performance mode shutdown mode v ddosc 2.35 ? 2.5 ? 2 2 high impedance output 2.75 ? v v 5 p low voltage reset 3 assert level 3 monitors v dd , always active v lv r a 2.25 ? ? v 6 c power-on reset 4 assert level deassert level 4 monitors v dd , always active v pora v pord 0.97 ? ? ? ? 2.07 v v electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 247 a.2.2 chip power-up and voltage drops voltage regulator sub modules por (power-on reset) and lvr (low vo ltage reset) handle chip power-up or drops of the supply voltage. their function is described in figure a-1 . figure a-1. voltage regulator ? chip power-up and voltage drops (not scaled) a.2.3 output loads a.2.3.1 resistive loads on-chip voltage regulator intended to supply the internal logic and oscill ator circuits allows no external dc loads. a.2.3.2 capacitive loads the capacitive loads are specified in figure a-10 . ceramic capacitors with x7 r dielectricum are required table a-10. voltage regulator recommended capacitive loads num characteristic symbol min typical max unit 1 vdd external capacitive load c ddext 200 440 12000 nf 3 vddosc external capacitive load c ddoscext 90 220 5000 nf v lvrd v lvra v pord por lvr t v v dd electrical characteristics mfr4300 data sheet, rev. 3 248 freescale semiconductor a.3 reset and oscillator this section summarizes the electri cal characteristics of the various startup scenarios for the oscillator. a.3.1 startup table a-11 summarizes several star tup characteristics explained in this section. detailed de scription of the startup behavior can be found in chapter 6, ?clocks and reset generator (crg) ?. a.3.1.1 por the release level v pord (see table a-9 ) and the assert level v pora (see table a-9 ) are derived from the v dd supply. they are also valid if the device is po wered externally. after releasing the por reset the oscillator is started. a.3.1.2 lvr the assert level v lvra (see table a-9 ) is derived from the v dd supply. after releasi ng the lvr reset, the oscillator is started.. a.3.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cc starts operations, if there was an oscillation before reset. table a-11. startup characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 t por deassert level v pord ? ? 2.07 v 2 t por assert level v pora 0.97 ? ? v 3 d reset input pulse width, minimum input time pw rstl 2??t osc electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 249 a.3.2 oscillator the device features an internal pier ce oscillator with a clock monitor. a clock monitor failure is asserted if the clock signal is below the cl ock monitor assert frequency, f cmfa . a.4 asynchronous memory interface timing the cc ami interface read/write timing diag ram is shown in the following figures. ? writing to the device is accomplished when chip enable (ce#) and write enable (we#) inputs are low (asserted). ? reading from the device is accomp lished when chip enable (ce# ) and output enable (oe#) are low (asserted) while the write enable (we#) is high (deasserted). ? the input/output pins d[15:0] are in a high-impedance state when th e device is not selected (ce# is high), the outputs are disabled (oe# high) or during a write operati on (ce# low, and we# low). table a-12. oscillator characteristics conditions are shown in ta b l e a - 4 unless otherwise noted num c rating symbol min typ max unit 1 c crystal oscillator range (pierce) 1 1 depending on the crystal a damping series resistor might be necessary f osc 0.5 ? 40 mhz 2 p startup current i osc 100 ? ? a 4 p clock monitor assert frequency f cmaf 50 100 200 khz 5 p external square wave input frequency f ext 0.5 ? 50 mhz 6 d external square wave pulse width low t extl 9.5 ? ? ns 7 d external square wave pulse width high t exth 9.5 ? ? ns 8 d external square wave rise time t extr ?? 1ns 9 d external square wave fall time t extf ?? 1ns 10 d input capacitance (extal, xtal pins) c in ?7?pf 11 c dc operating bias in pierce mode on extal pin v dcbias ?tbd?v electrical characteristics mfr4300 data sheet, rev. 3 250 freescale semiconductor figure a-2. ami interface read timing diagram 1 figure a-3. ami interface write timing diagram 2 1. ?ce# ?or? oe#? is a logical or of the chip enable (ce#) and output enable (oe#) inputs. 2. ?ce# ?or? we#? is a logical or of the chip enable (ce#) and write enable (we#) inputs. ce# ?or? oe# a[12:1] address t sar d[15:0] data t har t lzoe t hzoe t hoe t rc t doe t loe we# t weoe t oewe ce# ?or? we# a[12:1] address t saw d[15:0] data t haw t sd t hd t wc oe# t hwe t lwe t weoe t oewe bsel[1:0] byte select electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 251 table a-13. ami interface ac switching characteristics over the operating range 1 1 t ami_clk is the period in ns of the chi and host interface clock selected by if_sel[1:0] as described in ta b l e 2 - 6 . characteristic symbol min max unit read cycle read time cycle t rc 2.5 t ami_clk + 32 ns address setup read t sar 5ns address hold read t har 5ns oe# low to data valid t doe 2.5 t ami_clk + 23 ns oe# low time t loe 2.5 t ami_clk + 27 2 2 depends on duty cycle of the chi and host interface clock: t loe = (3.0 t ami_clk ) ? t ami_clk_high + 27, where t ami_clk_high is the period in ns of the high phas e of the chi and host interface clock. ns oe# high time t hoe 5ns oe# low to low-z t lzoe 5ns oe# high to high-z t hzoe 15 ns we# high to oe# low t weoe 1 t ami_clk ns write cycle write time cycle t wc 3 t ami_clk + 10 ns address setup write t saw 5ns address hold write t haw 5ns data setup t sd 5ns data hold t hd 5ns we# low time t lwe 1.5 t ami_clk + 5 ns we# high time t hwe 0.5 t ami_clk + 5 ns oe# high to we# low t oewe 0ns electrical characteristics mfr4300 data sheet, rev. 3 252 freescale semiconductor a.5 hcs12 interface timing figure a-4. hcs12 interface read timing diagram figure a-5. hcs12 interface write timing diagram eclk pad[15:0] address r/w t sa acs[2:0] data t ha t lec t hec t srw t dec t hdr t drw t hrw t sdr t hda xaddr[19:14] address eclk pad[15:0] address r/w t sa acs[2:0] data t ha t lec t hec t srw lstrb t ddw t hdw t drw t hrw xaddr[19:14] address t hls t dls t sls low strobe electrical characteristics mfr4300 data sheet, rev. 3 freescale semiconductor 253 table a-14. hcs12 interface ac switching characteristics over the operating range 1 1 based on f clk_cc = 40 mhz. characteristic symbol min max unit pulse width, eclk low t lec 30 ? ns pulse width, eclk high t hec 99 2 2 depends on duty cycle of extal/clk_cc: t hec = 99 + (t clk_cc 0.5) ? t clk_cc_high , where t clk_cc is the period in ns of extal/clk_cc and t clk_cc_high is the period in ns of the high phase of extal/clk_cc. ?ns address valid time to eclk rise t sa 11 ? ns write data delay time t ddw ?70ns write data hold time t hdw 80 ns rw delay time t drw ?7ns rw valid time to eclk rise t srw 14 ? ns rw hold time t hrw 2?ns data hold to address t hda 2?ns multiplexed address hold time t ha 2?ns eclk high access time (ecl k high to read data valid) t dec 50 90 ns read data setup time t sdr 13 ? ns read data hold time t hdr 0?ns low strobe delay time t dls ?7ns low strobe valid to eclk rise t sls 14 ? ns low strobe hold time t hls 2?ns electrical characteristics mfr4300 data sheet, rev. 3 254 freescale semiconductor package information mfr4300 data sheet, rev. 3 freescale semiconductor 255 appendix b package information b.1 64-pin lqfp package figure b-1. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 1) package information mfr4300 data sheet, rev. 3 256 freescale semiconductor figure b-2. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 2) package information mfr4300 data sheet, rev. 3 freescale semiconductor 257 figure b-3. 64-pin lqfp mechanical dimensions (case n 840f-02) (page 3) package information mfr4300 data sheet, rev. 3 258 freescale semiconductor printed circuit board layout recommendations mfr4300 data sheet, rev. 3 freescale semiconductor 259 appendix c printed circuit board layout recommendations the pcb must be laid out carefully to ensure prope r operation of the voltage regulator and the cc. the following rules must be observed: ? every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (cd). ? the central point of the ground star should be the vssr pin. ? low-ohmic low-inductance connections sh ould be used between vssx and vssr. ? vssosc must be directly connected to vssr. ? traces of vssosc, extal and xtal must be kept as short as possible. occupied board area for c1, c2, c3 and q should be as small as possible. ? other signals or supply lines should not be r outed under the area occupied by c1, c2, c3, and q and the connection area of the cc. ? the central power input should be fed in at the vdda/vssa pins. figure c-1 shows a recommended pcb layout (64-pin lqfp) for standard pi erce oscillator mode, while table c-1 provides suggested values fo r the external components. table c-1. suggested external component values component purpose type value c1 osc load cap ceramic x7r 2pf c2 osc load cap ceramic x7r 2pf c3 vddosc filter cap ceramic x7r 100? 220nf c4 vdda filter cap ceramic x7r 100? 220nf cd vddr, vddx filter cap cer amic x7r/tantalum 100? 220nf cload vdd2_5 filter cap ceramic x7r 100? 220nf r b osc resistance 1 m r s osc resistance 0 (i.e. short-circuit) q quartz ndk nx8045ga 40 mhz printed circuit board layout recommendations mfr4300 data sheet, rev. 3 260 freescale semiconductor figure c-1. recommended pcb layout (64-pin lqfp) for standard pierce oscillator mode cload cd cd cd cd cd c3 rs rb q c1 c2 vddx1 vssx1 vssr vddr vssosc vddosc vssx4 vddx4 vss2_5 vdd2_5 vddx3 vssx3 vdda vssa suggested component values: q: ndk nx8045ga ? 40mhz c1 = c2 = 2pf rb = 1m rs = 0 (i.e. short circuit) c3 = cload = 220nf cd = 100nf cd vddx2 vssx2 mfr4300 data sheet, rev. 3 freescale semiconductor 261 appendix d index of registers a associated functions 60 f features distinctive 59, 205, 221 functions associated 60 i initialization/application information 201, 203 m maximum ratings (electrical) 240 message buffer individual 134 r registers asic version number register (avnr) 208 channel a status error count er register (casercr) 87 channel b status error count er register (cbsercr) 87 chi error flag register (chierfr) 84 clock and reset status register (crsr) 223 combined interrupt flag register (cifrr) 96 cycle counter regi ster (cyctr) 94 detection enable register (der) 222 global interrupt flag and en able register (gifer) 77 host interface pins drive st rength register (hipdsr) 208 host interface pins pullup/down control register (hippcr) 211 host interface pins pullup/down enable register (hipper) 209 last dynamic transmit slot cha nnel a register (ldtxslar) 118 last dynamic transmit slot cha nnel b register (ldtxslbr) 119 macrotick counter re gister (mtctr) 94 message buffer configurat ion, control, status registers (mbccsrn) 128 index of registers mfr4300 data sheet, rev. 3 262 freescale semiconductor message buffer cycle counter f ilter registers (mbccfrn) 130 message buffer data si ze register (mbdsr) 74 message buffer frame id registers (mbfidrn) 131 message buffer index re gisters (mbidxrn) 132 message buffer interrupt vect or register (mbivec) 86 message buffer segment size and utilization re gister (mbssutr) 74 module configuration register (mcr) 68 module version register (mvr) 68 mts a configuration register (mtsacfr) 111 mts b configuration register (mtsbcfr) 111 network management vector length register (nmvlr) 102 network management vector registers (nmvr0?nmvr5) 101 offset correction value register (ofcorvr) 96 part id regist er (pidr) 208 physical layer pins drive st rength register (plpdsr) 209 physical layer pins pullup/down control register (plppcr) 213 physical layer pins pullup/down enable register (plpper) 212 protocol configuration register 0 (pcr 0) 121 protocol configuration register 1 (pcr 1) 121 protocol configuration register 10 (pcr10) 123 protocol configuration register 11 (pcr11) 124 protocol configuration register 12 (pcr12) 124 protocol configuration register 13 (pcr13) 124 protocol configuration register 14 (pcr14) 124 protocol configuration register 15 (pcr15) 125 protocol configuration register 16 (pcr16) 125 protocol configuration register 17 (pcr17) 125 protocol configuration register 18 (pcr18) 125 protocol configuration register 19 (pcr19) 125 protocol configuration register 2 (pcr2) 122 protocol configuration register 20 (pcr20) 126 protocol configuration register 21 (pcr21) 126 protocol configuration register 22 (pcr22) 126 protocol configuration register 23 (pcr23) 126 protocol configuration register 24 (pcr24) 126 protocol configuration register 25 (pcr25) 127 protocol configuration register 26 (pcr26) 127 protocol configuration register 27 (pcr27) 127 protocol configuration register 28 (pcr28) 127 protocol configuration register 29 (pcr29) 128 protocol configuration register 3 (pcr3) 122 protocol configuration register 30 (pcr30) 128 protocol configuration register 4 (pcr4) 122 protocol configuration register 5 (pcr5) 122 protocol configuration register 6 (pcr6) 122 index of registers mfr4300 data sheet, rev. 3 freescale semiconductor 263 protocol configuration register 7 (pcr7) 123 protocol configuration register 8 (pcr8) 123 protocol configuration register 9 (pcr9) 123 protocol configuration registers 119 protocol interrupt enable register 0 (pier0) 82 protocol interrupt enable register 1 (pier1) 83 protocol interrupt flag register 0 (pifr0) 79 protocol interrupt flag register 1 (pifr1) 81 protocol operation cont rol register (pocr) 75 protocol status register 0 (psr0) 88 protocol status register 1 (psr1) 89 protocol status register 2 (psr2) 90 protocol status register 3 (psr3) 92 rate correction value register (rtcorvr) 95 receive fifo a read index register (rfarir) 114 receive fifo b read index register (rfbrir) 115 receive fifo depth and si ze register (rfdsr) 114 receive fifo frame id reject ion filter mask register 117 receive fifo frame id rejection fi lter value register (rffidrfvr) 116 receive fifo message id acceptance fi lter mask register (rfmiafmr) 116 receive fifo message id acceptance fi lter value register (rfmidafvr) 115 receive fifo range filter conf iguration register (rfrfcfr) 117 receive fifo range filter c ontrol register (rfrfctr) 118 receive fifo selection register (rfsr) 113 receive fifo start inde x register (rfsir) 113 receive shadow buffer i ndex register (rsbir) 112 slot counter channel a register (sltctar) 95 slot counter channel b register (sltctbr) 95 slot status counter condi tion register (ssccr) 107 slot status counter re gisters (sscr0?sscr3) 110 slot status registers (ssr0?ssr7) 109 slot status selecti on register (sssr) 106 strobe port control register (stbpcr) 73 strobe signal control register (stbscr) 70 sync frame counter register (sfcntr) 98 sync frame id acceptance filter mask register (sfidafmr) 101 sync frame id acceptance filter value register (sfidafvr) 101 sync frame table configuration, cont rol, status regi ster (sftccsr) 99 sync frame table offset register (sftor) 98 timer 1 cycle set register (ti1cysr) 104 timer 1 macrotick offset register (ti1mtor) 104 timer 2 configuration register 0 (ti2cr0) 105 timer 2 configuration register 1 (ti2cr1) 106 timer configuration and c ontrol register (ticcr) 103 index of registers mfr4300 data sheet, rev. 3 264 freescale semiconductor document number: mfr4300 rev. 3 12/2006 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. |
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